Jairo Andres Velasco Romero
Apparently, this user prefers to keep an air of mystery about them.
8 Can someone break down how this receiver works? Dec 20 '11
6 How does a PLL inside a FPGA work? May 25 '11
3 DS1307 power failure problem Jan 8 '13
1 Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap? Aug 30 '15
0 Can I use LPDDR with Cyclone III FPGA? Sep 15 '12