Jairo Andres Velasco Romero
Apparently, this user prefers to keep an air of mystery about them.
8 Can someone break down how this receiver works? dec 20 '11
6 How does a PLL inside a FPGA work? may 25 '11
3 DS1307 power failure problem jan 8 '13
1 Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap? aug 30
0 Can I use LPDDR with Cyclone III FPGA? sep 15 '12