User Randomblue - Electrical Engineering Stack Exchange

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	2,767 reputation	bio	website		visits	member for	1 year, 7 months
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18

votes

1

answer

543

views

Why is “silkscreen” called that way?

pcb-fabrication silkscreen

mar 1 at 3:25 Community♦ 1

14

votes

2

answers

387

views

Why are copper tracks orange-gold?

pcb copper

feb 21 at 2:16 Chetan Bhargava 2,600

11

votes

5

answers

6

kviews

Why do GPS receivers have a 1 PPS output?

gps

apr 27 '12 at 1:42 Tony Stewart 1

1

10

votes

3

answers

412

views

Is electronics driven by scientific papers?

theory

aug 11 at 4:53 mctylr 1,113

2

10

votes

2

answers

746

views

GPS: 12 satellites in view but no fix

gps

jun 20 '12 at 14:19 Axeman 2,705

3

9

votes

4

answers

512

views

Effective number of bits of 14-bit ADC

adc

apr 20 at 23:54 DrFriedParts 4,562

1

9

votes

2

answers

676

views

Programming multiple FPGAs using JTAG

fpga jtag spartan

jul 19 at 12:18 Randomblue 2,767

8

votes

1

answer

165

views

Is a 10GHz clock required to drive a 10Gb serial pin?

serial ethernet clock-speed

dec 3 at 15:13 Some Hardware Guy 3,519

1

8

votes

2

answers

305

views

Can FPGAs dynamically modify their logic?

fpga

oct 20 at 22:44 Dave Tweed 19.5k

1

8

votes

2

answers

257

views

How do commercial microprocessors meet timing with a gigahertz clock?

fpga microprocessor timing

sep 12 at 18:06 ajs410 4,122

8

votes

2

answers

543

views

What is a false path timing constraint?

fpga timing hdl

aug 30 at 21:01 Oli Glaser 34k

8

votes

4

answers

2

kviews

Why are inferred latches bad?

verilog hdl latch

aug 23 at 19:22 supercat 13.7k

1

8

votes

2

answers

376

views

What are sacrificial components?

terminology

jul 28 at 11:16 stevenvh 85.8k

7

votes

1

answer

113

views

What does O stand for in V_CBO and V_CEO?

transistors datasheet

feb 17 at 22:04 jippie 9,414

3

7

votes

1

answer

3

kviews

Push-pull/open drain; pull-up/pull-down

microcontroller gpio

jul 28 at 14:08 stevenvh 85.8k

1

7

votes

1

answer

294

views

Meaning of hash symbol in pin name

pins

jun 12 '12 at 16:11 clabacchio♦ 7,346

6

votes

0

answers

175

views

What is the “loaded resistor” for ultrasonic receivers?

resistors ultrasound

apr 12 at 3:54 Community♦ 1

6

votes

4

answers

199

views

Time of flight difference in hardware

microprocessor ultrasound time pulse difference

dec 21 at 22:31 Randomblue 2,767

6

votes

2

answers

255

views

Specify exact pin locations on FPGA

fpga altera pin

sep 18 at 20:20 Randomblue 2,767

1

6

votes

2

answers

465

views

What is a brownout condition?

dac brownout

aug 10 at 14:06 stevenvh 85.8k

3

6

votes

2

answers

353

views

What is a mutator?

theory gyrator memristor

jul 29 at 18:16 zebonaut 8,570

1

6

votes

3

answers

505

views

Why would an input pin have both a pull-up and pull-down resistor?

resistors pullup pulldown gpio

jul 29 at 8:08 Jayprakash Shet 63

6

votes

3

answers

539

views

What electronic component of a computer produces (sound) noise?

sound

jul 28 at 20:02 Tony Stewart 1

6

votes

1

answer

410

views

Verilog: XOR all signals of vector together

verilog

jul 5 at 14:22 Thorn 1,390

6

votes

1

answer

195

views

Preventing Verilog module from being optimised away

verilog spartan ise

jun 27 at 15:49 Thorn 1,390

6

votes

1

answer

214

views

EEPROM: Same driver for similar chips, different behaviours

stm32 eeprom

jun 20 '12 at 16:00 embedded.kyle 4,823

1

6

votes

2

answers

2

kviews

STM32F2: Makefile, linker script and start-up file combination without commercial IDE

c stm32 gcc

may 5 '12 at 2:20 dwelch 1,577

1

6

votes

3

answers

597

views

What happens when an FPGA is “programmed”?

fpga hdl

apr 24 '12 at 17:17 Brian Carlton 9,076

5

votes

4

answers

1

kviews

What is dual/quad I/O?

spi flash

may 9 at 5:12 Camil Staps 4,264

5

votes

1

answer

158

views

Altera: Change JTAG clock speed

fpga altera cyclone

jan 17 at 5:05 Oli Glaser 34k

Randomblue

182 Questions