Apparently, this user prefers to keep an air of mystery about them.
5 What back-end and front-end are in hardware design? apr 23 '12
4 Linearized phase domain model of a PLL - what does a ratio of input phase over output phase mean? jan 19 '12
3 How will this Verilog line be synthesized? dec 7 '11
2 What is S/P and P/S converter in communication? mar 3 '12