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Socrates
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46
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4
What is the I/O standard for the PCIe data lines?
3
How fast does a 64-bit multiply or divide execute on an FPGA?
3
My design is not meeting timing. What can I do?
3
Is there any restriction in the choice of Ethernet PHY, depending on the TCP/IP stack?
3
Merge a differential pair into one signal
2
I am not able to instantiate sub modules inside always block
2
Taking output from FIFO implemented in verilog
2
How to safely discharge high voltage (> 42 V) capacitors?
2
How to generate wait until division is over in verilog?
2
How do I select pins in Quartus 2?
2
Is it possible to build something that can measure water and oil in a tank with out being in the tank?
2
Why are vias placed this way on a PCB?
2
Tiny ARM Development Board?
2
Drive LEDs from USB
1
what is a transceiver reconfiguration controller on FPGA
1
Custom SOPC Builder Components in Quartus II
1
VHDL SRAM Controller interface
1
Without double-clocking, how to perform 2 write and 2 read each clock using Dual Port RAM?
1
View more than 100 worst-case paths in Quartus II
1
First project with LPC1769
1
LDO or switching Regulator
1
RF current output from microcontroller?
1
Connecting 3.3 and 5 V devices
1
Can I use LPDDR with Cyclone III FPGA?
1
Linux PCB with support for GPU accelerated X Windows
1
MCUs programmable by USB or ethernet
1
Why do I get a failure in Quartus while trying to programming my FPGA?
1
Stress testing an FPGA's power supply
1
Crazy homebrew 500 MHz 1 Gs/s oscilloscope possible?
1
Aluminum project box: should BNC conenctors touch it?
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