User John Burton - Electrical Engineering Stack Exchange

John Burton

Member for 14 years
Last seen more than a month ago

this.domain.name
United Kingdom

25 Questions

Score Activity Newest Views

20 votes

10 answers

7k views

Safety of making PCBs

asked Jul 15, 2010 at 11:16

17 votes

8 answers

6k views

What if I overload a cheap AC adaptor?

asked Jun 10, 2010 at 15:43

14 votes

2 answers

2k views

Generating PAL tv signal using a PIC

asked Jun 18, 2010 at 12:44

12 votes

3 answers

4k views

Oscilloscope trace not quite square

asked Jan 16, 2012 at 11:39

10 votes

5 answers

6k views

Battery life monitor on PIC circuit

asked May 18, 2010 at 13:56

10 votes

2 answers

26k views

Driving LED strip from microcontroller

asked May 1, 2013 at 11:12

9 votes

4 answers

1k views

Building a circuit with LPC1343

asked Jul 9, 2010 at 17:32

9 votes

1 answer

27k views

Birectional I/O pin in verilog

asked Jun 3, 2012 at 14:43

8 votes

3 answers

11k views

Raspberry Pi as JTAG programmer?

asked Dec 10, 2012 at 9:58

7 votes

2 answers

14k views

Implement serial port on fpga (verilog)

asked May 1, 2011 at 13:37

7 votes

1 answer

2k views

Reflow soldering issues

asked Nov 16, 2016 at 23:09

7 votes

5 answers

8k views

VGA to HDMI converter

asked Jun 20, 2011 at 7:39

7 votes

2 answers

2k views

Using 240v mains on/off as input to microcontroller

asked Sep 12, 2017 at 10:53

6 votes

3 answers

2k views

Interfacing static ram to fpga

asked Jun 9, 2012 at 9:38

5 votes

1 answer

3k views

Other name for VGA socket?

asked Feb 28, 2012 at 9:02

5 votes

2 answers

2k views

Beginner with fpga and timing issues

asked Apr 12, 2011 at 7:41

3 votes

3 answers

221 views

Speed of various prototype systems for digital electronics

asked May 7, 2011 at 8:32

3 votes

2 answers

334 views

Protecting fpga / ram against mistakes

asked Mar 2, 2012 at 20:11

2 votes

1 answer

396 views

Reset signal for fpga evaluation board

asked May 3, 2011 at 10:37

2 votes

3 answers

2k views

RAM device / timings for small VGA project

asked May 6, 2011 at 9:49

2 votes

2 answers

847 views

Combining components and timing in VHDL (And probably verilog) / FPGA

asked Sep 4, 2015 at 10:12

1 vote

1 answer

773 views

Interfacing memory to papilio fpga board

asked Jan 21, 2012 at 14:33

1 vote

1 answer

162 views

Sending data to CPLD

asked Dec 10, 2012 at 8:55

0 votes

1 answer

492 views

Problem compiling verilog

asked Dec 20, 2012 at 15:16

0 votes

2 answers

99 views

Are these 433Mhz receivers likely to be able to physically receive signal from this? [closed]

asked Dec 1, 2016 at 11:09