Vlad Lazarenko

673 reputation

213

bio	website	lazarenko.me
	location	New York, NY
	age
visits	member for	1 year, 2 months
	seen	7 hours ago
stats	profile views	61

Hi there! My name is Vlad. I am a technologist primarily engaged in low-latency trading systems development with a market-making company here in New York City. I live in both software and hardware worlds, work primarily with x86_64 Intel architectures and FPGAs. Write mostly C, C++ and Verilog, but can easily do an iPhone app in Objective-C, for example. My home page/blog is http://lazarenko.me. Have a great day!

	673 reputation	bio	website	lazarenko.me	visits	member for	1 year, 2 months
213 badges		location	New York, NY		seen	7 hours ago

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8 Answers

votes activity newest

17	FPGA programming, where to begin
5	Specify include path in Quartus II
5	Altera optimisation: “Stuck at GND due to stuck port data_in”
4	What is a typical example of a combinatorial feedback loop?
3	Verilog - Referencing Flattened Busses in Module Instantiation

673 Reputation

+20	Specify include path in Quartus II
+10	Altera optimisation: “Stuck at GND due to stuck port data_in”
+20	Open Source verilog synthesizer
+10	FPGA programming, where to begin

4 Questions

votes activity newest

4	Flip-flop vs combinatorial description - what exactly is the difference?
4	Help wanted explaining signals coming with higher frequency than clock and how to handle them
3	Unsigned addition overflow and synthesis
0	Working with Spartan-6 LX9 clock