$random in Verilog doesn't seem to be working

Question

In Verilog, $random generates different random inputs but this doesn't seem to be working when I try. Each time I use $random for a reg or integer, I must be getting different different values but that is not so. I tried it even in Modelsim simulator.

http://www.edaplayground.com/x/Umt

`timescale 1ns/1ns
module tt;
integer kk;

initial
begin
  repeat(5) begin
    kk=$random % 10;
  end
  $monitor("%d",kk);
end
endmodule

Answer 1

If you output all 5 random values you generate you can see that you get different values: EDA Playground.

The point of a seed is, given the same seed you can generate the same sequence. This allows you to have randomised tests but when one instance fails you can plugin the seed that was used and rerun the same test.

module tt;
  integer kk;
  integer seed = 1; //change this for different sequence
  initial
    begin
      repeat(5) begin
        kk=$random(seed) % 10;
        $display("%d",kk);
      end
    end

endmodule

Answer 2

Your problem is that you are generating 5 random values with 0 delay, and $monitor only prints a single line once per time slot when one of its arguments change. You should not be using $monitor except for rare debugging cases.

Also, I suggest that you use $urandom instead of $random. The seed for $urandom can be changed on the simulator command line without having to recompile. You can even select a random seed so that every time you simulate, it will use a new random seed (in ModelSim: -sv_seed random). $urandom has random stability that would be very difficult to achieve using $random. Random stability lets you make certain changes to your testbench and re-run the simulation with the same seed without disturbing the random numbers generated. This makes debugging much more predictable. See section 18.14 of the IEEE Std 1800-2012 LRM.