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I'm working on a PCB layout for two high side switches. You can see below a picture of my current layout.

PCB layout

The copper weight of the future PCB will probably be 2 oz/ft² (double sided). I use two p-channel MOSFET(IPB180P04P4). I expect 10 Amps for the MOSFET on the right (I choose to be very close to the minimal footprint, Pd about 0.2 W) and 15 Amps (U2, peak at 30 Amps, Pd about 0.45 W, max 1.8 W) for the MOSFET on the left (U1, 8 cm² of copper).

IC1 is a current sensor.

The terminal blocks (U15, U16) are of this type: WM4670-ND on Digikey.

To draw that much current on this type of PCB, one of the calculator online told me I needed 20 mm traces. To save some space, I decided to split this large trace into two traces (one on the top, one on the bottom). I connect both traces with a pattern of vias (drill size 0.5 mm on a grid of 2x2 mm²). I don't have any experience in this kind of layout so I looked at other boards and picked up a dimension which seemed fair to me. Is this via pattern the right way to go ?

Under the MOSFETs, I use the same kind of pattern but with a smaller drill size 0.3 mm to make the thermal junction. Does the solder will flow better with this size ? None of the vias are filled so far...

I'm also thinking about not having any solder mask on these traces, that would be to apply some solder on the copper.

I'm also concerned about the pads of the MOSFETs. I did choose not to cover them with copper. I thought the device could self-centered this way but that may probably increase the resistance...

Please feel free to comment the layout !
Thank you !

EDIT 1

I slightly improve the design. I added more vias under the thermal pads of the MOSFETs. There is some bare copper under the MOSFETs (if I want to add a heatsink in the future).

Top v2

Please feel free to comment ! Thank you in advance !

EDIT 2

A new update to this design. I increased the copper area around the leads of the MOSFETs. That should decrease the resistance of these traces.

I added more vias between the top and bottom layers to improve the current distribution in these layers.

I asked the manufacturer if I could have plugged vias under the devices to improve the heat dissipation. He told me that was duable.

I don't think I will change anything else. That was kind of my best guess so I may give it a go if nobody has any comment.

Top Bottom v3 Bottom v3

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    \$\begingroup\$ A couple of things: First, you really don't want many (or any) vias directly under your MOSFETs. Either you'll have to pay extra for the board house to plug them, or they'll wick the solder away from the part (or worse, if the vias are tented on the bottom, the escaping flux fumes can make big voids right under the FET). I would recommend extending the copper area around the FET pad (like you did to the left of U$2) and add more vias there. Also, while solder-on-unmasked-traces can help, it'll add an extra manufacturing step. It'll matter if you're cost-sensitive. Looks like a fun project! \$\endgroup\$
    – bitsmack
    Mar 6, 2015 at 0:46
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    \$\begingroup\$ Yes, it is a fun project !! Thank you for the comments, the manufacturer is already making the boards. I will definetely pay attention to these issues. I'm worried about the vias under the MOSFETs. They are not plugged, but I expect they don't wick too much the solder away from the part. I talked about this problem in another question. About putting some solder on unmasked traces, I thought about it and decided that could work out without. That also reduces the chance of short-circuit which is not a bad thing... \$\endgroup\$
    – Marmoz
    Mar 7, 2015 at 6:07
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    \$\begingroup\$ The advice that I've always gotten is to "never" use open vias in a pad. Sometimes I need to, so I put in a few, and it has worked out so far. They do wick solder! I made a board once with lots of these (less than you have, though (grin)), and the solder ran to the underside of the board and pooled in one big drop. Even though there was soldermask between the bottom-layer vias! An attempt to solve this problem is to "tent" the vias on the bottom layer. This means that they are covered over with soldermask. It only is possible if the vias are small enough to keep the mask intact... \$\endgroup\$
    – bitsmack
    Mar 7, 2015 at 7:18
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    \$\begingroup\$ The problem with this, however, is that expanding gasses (either the air itself, or from the flux) can't escape through the bottom of the board. They push up against the FET, leaving bubbles and voids. Not a good solution. If I were in your place, with the boards already being manufactured, I would probably run solder into the vias manually, before soldering the FETs. Hopefully it won't run out of the bottom :) \$\endgroup\$
    – bitsmack
    Mar 7, 2015 at 7:19
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    \$\begingroup\$ Interesting to hear that you do not suggest vias under pads for dissipating heat. I worked with some power LEDs a while back and Cree specifically suggested adding vias under the pads to increase the area that can transfer the heat. I do understand the gasses expanding! Would be interested in the final conclusion! \$\endgroup\$
    – AJBotha
    Mar 13, 2015 at 13:52

3 Answers 3

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I'm curious how you derived your power dissipation numbers. Looking at the data sheet it looks like 10ams 200 mW (12 degree temperature rise), 30 amps, 2.5W with a 90 degree temperature rise (given the Rthja of 40 degrees/W which seems to be true even if you have 6 cm^2 of PCB area).

That said, if you want to pull a lot of heat out of your FETs you can have a .250" plated through hole drilled under them and then use a copper slug which extends up through the hole and contacts the back of the package. you could also glue a heat sink to the top but it is not as effective trying to conduct through the case.

To your layout questions, it looks like a 6mil trace for all of the source leads. That would be a poor choice at 30A, by comparison look inside a 30A fuse :-) What it means is that you'll get some warming on that trace. What ever trace width you pick, do the calculation at your chosen copper level and use current squared x resistance to compute how many watts that trace will dissipate.

You don't need a all the vias you've got on the pad. 5 would be sufficient to thermally connect top to bottom. I've seen people just use one, but you rely heavily on the plate though of the hole in that case.

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  • \$\begingroup\$ Actually, most of the current goes from the IN block to the OUT block, they are terminal blocks. I should go through the number again, I don't have them in mind right now but that worked fine at the end. I'm not sure to understand the copper slug trick... OK for all the vias, I didn't really know so I tried this way. Good to know for next time, thank you ! \$\endgroup\$
    – Marmoz
    Jul 3, 2016 at 22:08
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You could consider removing the solder mask over the high current traces and allowing the hasl coating to thicken them a little (and possibly fill the vias?).

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  • \$\begingroup\$ Does anyone still use HASL? A lot of PCB manufacturers don't even support HASL anymore since the cost difference is virtually none, and ENIG produces a better, flatter finish. \$\endgroup\$
    – Oliver
    May 22, 2015 at 11:20
  • \$\begingroup\$ I can just tell that they actually did a ENIG finish. However, I didn't remove the solder mask but that was a good point. Thank you \$\endgroup\$
    – Marmoz
    Jul 3, 2016 at 22:22
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Consider using an aluminum substrate PCB if you need this much cooling power. That is a LOT of thermal vias, I don't think many proto shops will make this without an additional drilling charge.

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  • \$\begingroup\$ General comment in case it helps someone: a lot of places draw a line at 35 drills per square inch. \$\endgroup\$
    – Anthony
    Aug 9, 2015 at 22:55
  • \$\begingroup\$ I didn't know the aluminum substrate PCB at the time. But that finally worked out. I saw commercial PCBs for high currents with these much vias, so I thought that couldn't harm. I don't actually know if they charged me any additional fees, they don't say anything on the quotation... but that does not mean they did not charge me I guess. \$\endgroup\$
    – Marmoz
    Jul 3, 2016 at 22:17

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