Is this clamping voltage divider for a high-impedance input a good, robust design?

Question

I have an AC input as follows:

1. Can range from ±10V to at least ±500V continuously.
2. Runs from roughly 1 Hz to 1 kHz.
3. Needs > 100 kΩ of impedance on it, otherwise its amplitude changes.
4. May occasionally be disconnected and subject the system to ESD events.

When the input is below 20V, I need to digitize the waveform with an ADC. When it is above 20V, I can ignore it as out of range, but my system needs to not be damaged.

Since my ADC needs a relatively stiff signal, I wanted to buffer the input for further stages (in those, I will bias it, clamp it to 0V to 5V, and feed it to an ADC).

I designed the following circuit for my initial input stage to get a safe, strong output that I can feed to further stages:

^{simulate this circuit – Schematic created using CircuitLab}

My goals are:

1. Ensure > 100 kΩ of impedance on the source.
2. Change a ±20V input to roughly a ±1.66V output.
3. Provide a stiff output.
4. Safely handle continuous high-voltage inputs (at least ±500V).
5. Handle ESD events without dumping much current/voltage onto the ±7.5V rails.

Here is my rationale for my circuit design:

1. R1 and R2 form a voltage divider, reducing the voltage by 12X.
2. The TVS diode reacts quickly to protect against ESD events on the input, dumping them to my strong ground, without dumping anything onto my (weak) ±7.5V rails.
3. The TVS diode also handles extreme overvoltage (sustained ±500V) by shunting to ground. It is past R1 to limit current in these cases.
4. D1 and D2 clamp the divided voltage to ±8.5V so I don't need a high-voltage capacitor for C1; being after R1, the current through them is also limited.
5. C1 decouples the input signal. It will be a bipolar electrolytic. It needs to have a relatively large capacitance to allow the 1 Hz signals to pass unaffected: $$\frac{1}{2 \pi R_2 C_1} \ll 1 \text{ Hz}$$ $$C_1 \gg \frac{1}{2 \pi \times 1 \text{ Hz}\times220 \text{ k}\Omega} = 8 \mu\text{F}$$
6. R3 and C2, with R3=R1, compensate for input current bias and offset in the op-amp (rather than just shorting the output to the negative input); also form a low-pass filter: $$f_c= \frac{1}{2 \pi R_3 C_2} = 36 \text{ kHz}$$

Is this circuit optimal for my goals? Can I expect any problems with it? Are there any improvements that I should make, or is there a better way to accomplish my goals?

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EDIT 1

1. I'd originally said this needed to handle ±200V continuously, but I think ±500V is a safer target.

2. In order for the TVS diode to work as is, R1 needs to be split into two resistors, here R1a and R1b, as suggested by @jp314:

^{simulate this circuit}

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EDIT 2

Here is a revised circuit that incorporates the suggestions received so far:

1. Zeners across the power supply (@Autistic).
2. Resistors leading into them (@Spehro Pefhany).
3. Fast BAV199 diodes (@Master; a lower-leakage alternative to the BAV99 that @Spehro Pefhany suggested, albeit with a maximum capacitance of around 2 pF rather than 1.15 pF).
4. TVS diode out front and upgraded to 500 V (@Master), so it handles only ESD events, protecting R1.
5. Dead short from op-amp output to negative input (@Spehro Pefhany and @Master).
6. Decreased C1 to 10μF (@Spehro Pefhany); this introduces a 0.3% voltage drop at 1 Hz which isn't as good as original the 220μF cap, but will make sourcing the capacitor easier.
7. Added 1 kΩ resistor R6 to limit the current into OA1 (@Autistic and @Master).

^{simulate this circuit}

Answer 1

Your D1 & D2 will take the input surges, not the TVS -- split the 220k to 200k + 20k, and put the 20k portion between the TVS and the diodes.

Or just use a 4.7 V zener from that node to GND.

Answer 2

You don't need R3/C2. The non-inverting op-amp input 'sees' R2 (20K) on the bias current DC path (not 220K), so the offset will likely be negligible if you replace it with a short. If you insist on R3/C2, see below for the calculation.

The 220K represents capacitive reactance of 0.7uF at 1Hz, so I think a small and inexpensive (and non-leaky) 10uF ceramic capacitor will be just fine, adding, in quadrature, about 7%, so a total effect of less than 0.3%. However there may be some effects because of the clamping, so best to investigate this depending on how exactly you expect it to behave. When clamping it 'sees' the 20k in series with the low impedance clamp, so the time constant is 11x shorter.

R1 is critical for reliability- virtually all the voltage gets dropped across it- it must be a high voltage type, rated to withstand whatever transients you expect, especially if this input voltage is coming from the mains that may mean a couple kV. Vishay VR25 may be suitable (leaded). Don't skimp here. Unless the last few pennies are more important than reliability, I'm not a big fan of using multiple ordinary resistors for this purpose either- one properly rated part should be okay unless you need to use two properly rated resistors in series for even more reliability.

I would lose the TVS and consider clamping either directly with a shunt (such as a zener pair) or low-capacitance switching diodes like a BAV99 pair to pre-biased shunts, such as Zeners or TL431s (with resistors to the supply rails). The latter will have much less capacitance than using zeners directly and will thus cause less phase shift at 1kHz, if that is important to you. The clamping current is less than 1mA at 200V in, so it's not very taxing, so long as R1 holds up against whatever EMF it is subject to. Both the options I suggested can easily clamp 100mA, at least for a brief time.

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R3/C2 do not really form a low pass filter- R3 and the input capacitance of the op-amp form a low pass filter, and C2 would ideally be chosen to be much larger, so if the input capacitance is 15pF you might use 1nF or something like that. You would only run into trouble with 20K alone if you had a wildly inappropriate op-amp (capable of very high frequencies) where the resulting phase shift affected the stability, and of course a short does not have that problem.

Answer 3

^{simulate this circuit – Schematic created using CircuitLab}

The P/N of OP AMP and diodes on schematics mean nothing. Diodes D3 D4 are either one BAV199 or 2 Gate to Channel junctions of jFET MMBF4117. OA1 is OPA365. C3 must be selected to provide sufficiently low pass frequency for filter on C3, R1/2.

R2 and R3 are preferably precise thin film resistors or even two parts of one resistor network. They define your zero drift.

R5 must be rated for 1 kV voltage, you can use several 0603 resistors in series.

And, to be really safe, you can add some 1 kOhm resistor between non-inverting input of OPA365 and mid-point of R1 R2. It helps limit the input current if something goes really bad.

The high power voltage limitor (like TVS diode or varistor) is preferably connected between INPUT and GND. Its voltage is about 600-800 V.

Answer 4

What kind of OPA do you use? If it is FET input OP AMP (input currents below 100 pA) then you do not need R3 C2. Also, if you do not care about DC offset, it is much better to remove R3 C2.

I see no value in TVS diode 30 V. Absolutely agree with @Autistic. You can put it straight in parallel to the input (before R1) and change to 500-700 V type. Its function then is: to protect R1 and other electronics from really short spikes over 800 V (I do not know if your application can get into this kind of trouble).

R1 must be either rated for 1000 V or implemented as a series of 0603 or larger resistors, taking isolation gaps into account.

As for "real" clamp: the idea of @Spehro Pefhany of pre-biased BAV199 (two low leakage diodes in one SOT package) looks the best. I would not care too mush about currents to power rails: they are limited by 4 mA (800 V / 200 kOhms), it is probably less than power supply current of one OP AMP you use.

Why not to put R2 (I believe it is a voltage dividor) before C1 and to use very large resistor (1 MOhm) on place of R2 - this allows C1 to be as small as few uF.