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I'm trying to design the following circuit:
The circuit should have a constant delay for any input size. However, when I change the input size from 10 bits to 12 bits, the circuit becomes slower.
The code might look like a full adder, but the carry out is only used for the next sum, so it doesn't propagate all the way through. I expected the same delay, how can I solve this?
For the speed I look at Fmax shown in Quartus II.

Code 10 bits: 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_RBSD is
    port(
        a, b : in STD_LOGIC_VECTOR(9 downto 0);
        sum : out STD_LOGIC_VECTOR(9 downto 0);
        clk, cin : in STD_LOGIC;
        cout : out STD_LOGIC
    );
end entity;

architecture behavioral of generic_RBSD is
    signal a_s, b_s, sum_s : STD_LOGIC_VECTOR(9 downto 0);
    signal couts : STD_LOGIC_VECTOR(4 downto 0);
begin
    couts(0) <= ((a_s(1) xor a_s(0)) and b_s(1)) or (a_s(1) and a_s(0)); 
    sum_s(1 downto 0) <= ((a_s(1) xor a_s(0) xor b_s(1) xor b_s(0)) or ((a_s(1) xor a_s(0) xor b_s(1)) and b_s(0))) & not(a_s(1) xor a_s(0) xor b_s(1) xor b_s(0));

    couts(1) <= ((a_s(3) xor a_s(2)) and b_s(3)) or (a_s(3) and a_s(2)); 
    sum_s(3 downto 2) <= (((a_s(3) xor a_s(2) xor b_s(3) xor b_s(2)) and couts(0)) or ((a_s(3) xor a_s(2) xor b_s(3)) and b_s(2))) & (a_s(3) xor a_s(2) xor b_s(3) xor b_s(2) xor couts(0));

    couts(2) <= ((a_s(5) xor a_s(4)) and b_s(5)) or (a_s(5) and a_s(4)); 
    sum_s(5 downto 4) <= (((a_s(5) xor a_s(4) xor b_s(5) xor b_s(4)) and couts(1)) or ((a_s(5) xor a_s(4) xor b_s(5)) and b_s(4))) & (a_s(5) xor a_s(4) xor b_s(5) xor b_s(4) xor couts(1));

    couts(3) <= ((a_s(7) xor a_s(6)) and b_s(7)) or (a_s(7) and a_s(6)); 
    sum_s(7 downto 6) <= (((a_s(7) xor a_s(6) xor b_s(7) xor b_s(6)) and couts(2)) or ((a_s(7) xor a_s(6) xor b_s(7)) and b_s(6))) & (a_s(7) xor a_s(6) xor b_s(7) xor b_s(6) xor couts(2));

    couts(4) <= ((a_s(9) xor a_s(8)) and b_s(9)) or (a_s(9) and a_s(8)); 
    sum_s(9 downto 8) <= (((a_s(9) xor a_s(8) xor b_s(9) xor b_s(8)) and couts(3)) or ((a_s(9) xor a_s(8) xor b_s(9)) and b_s(8))) & (a_s(9) xor a_s(8) xor b_s(9) xor b_s(8) xor couts(3));    

    process(all)
    begin
        if (rising_edge(clk)) then      
            a_s <= a;
            b_s <= b;
            sum <= sum_s(8 downto 0) & cin;
        end if;
    end process;
end architecture;

Code 12 bits: 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_RBSD is
    port(
        a, b : in STD_LOGIC_VECTOR(11 downto 0);
        sum : out STD_LOGIC_VECTOR(11 downto 0);
        clk, cin : in STD_LOGIC;
        cout : out STD_LOGIC
    );
end entity;

architecture behavioral of generic_RBSD is
    signal a_s, b_s, sum_s : STD_LOGIC_VECTOR(11 downto 0);
    signal couts : STD_LOGIC_VECTOR(5 downto 0);
begin
    couts(0) <= ((a_s(1) xor a_s(0)) and b_s(1)) or (a_s(1) and a_s(0)); 
    sum_s(1 downto 0) <= ((a_s(1) xor a_s(0) xor b_s(1) xor b_s(0)) or ((a_s(1) xor a_s(0) xor b_s(1)) and b_s(0))) & not(a_s(1) xor a_s(0) xor b_s(1) xor b_s(0));

    couts(1) <= ((a_s(3) xor a_s(2)) and b_s(3)) or (a_s(3) and a_s(2)); 
    sum_s(3 downto 2) <= (((a_s(3) xor a_s(2) xor b_s(3) xor b_s(2)) and couts(0)) or ((a_s(3) xor a_s(2) xor b_s(3)) and b_s(2))) & (a_s(3) xor a_s(2) xor b_s(3) xor b_s(2) xor couts(0));

    couts(2) <= ((a_s(5) xor a_s(4)) and b_s(5)) or (a_s(5) and a_s(4)); 
    sum_s(5 downto 4) <= (((a_s(5) xor a_s(4) xor b_s(5) xor b_s(4)) and couts(1)) or ((a_s(5) xor a_s(4) xor b_s(5)) and b_s(4))) & (a_s(5) xor a_s(4) xor b_s(5) xor b_s(4) xor couts(1));

    couts(3) <= ((a_s(7) xor a_s(6)) and b_s(7)) or (a_s(7) and a_s(6)); 
    sum_s(7 downto 6) <= (((a_s(7) xor a_s(6) xor b_s(7) xor b_s(6)) and couts(2)) or ((a_s(7) xor a_s(6) xor b_s(7)) and b_s(6))) & (a_s(7) xor a_s(6) xor b_s(7) xor b_s(6) xor couts(2));

    couts(4) <= ((a_s(9) xor a_s(8)) and b_s(9)) or (a_s(9) and a_s(8)); 
    sum_s(9 downto 8) <= (((a_s(9) xor a_s(8) xor b_s(9) xor b_s(8)) and couts(3)) or ((a_s(9) xor a_s(8) xor b_s(9)) and b_s(8))) & (a_s(9) xor a_s(8) xor b_s(9) xor b_s(8) xor couts(3));

    couts(5) <= ((a_s(11) xor a_s(10)) and b_s(11)) or (a_s(11) and a_s(10)); 
    sum_s(11 downto 10) <= (((a_s(11) xor a_s(10) xor b_s(11) xor b_s(10)) and couts(4)) or ((a_s(11) xor a_s(10) xor b_s(11)) and b_s(10))) & (a_s(11) xor a_s(10) xor b_s(11) xor b_s(10) xor couts(4));

    process(all)
    begin
        if (rising_edge(clk)) then      
            a_s <= a;
            b_s <= b;
            sum <= sum_s(10 downto 0) & cin;
        end if;
    end process;
end architecture;
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  • 3
    \$\begingroup\$ Bigger circuit = routing pressure + larger area = slower. \$\endgroup\$
    – Tom Carpenter
    Jul 17, 2016 at 20:45
  • \$\begingroup\$ This level of modelling is not taking into account routing or area. Or is the OP running synthesis/P+R on this RTL, then timing it? \$\endgroup\$
    – jbord39
    Jul 17, 2016 at 22:19
  • 1
    \$\begingroup\$ How are you measuring the delay? In simulation, or in real life? \$\endgroup\$
    – uint128_t
    Jul 17, 2016 at 22:47
  • \$\begingroup\$ When theoretically timing circuits (for example for research purposes) do you have to take that into account? I'm trying to design the same thing as on this site: louif.com/rbin When his input size increases, the delay doesn't. \$\endgroup\$
    – gilianzz
    Jul 17, 2016 at 22:48
  • \$\begingroup\$ In Quartus II I look at Fmax which says how fast this will run. \$\endgroup\$
    – gilianzz
    Jul 17, 2016 at 22:49

1 Answer 1

Reset to default
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I'm guessing that the author of http://www.louif.com/rbin/ ran the timing report with interconnect delays set to zero, which would mean the only delays taken into account were the combinatorial logic. A real-world implementation will have different delays due to place-and-route as other commenters have pointed out.

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  • \$\begingroup\$ So when you want to make the design open source and want to show the speed of the design, do you set interconnect delays to zero or not? \$\endgroup\$
    – gilianzz
    Jul 18, 2016 at 18:40
  • \$\begingroup\$ I would put the statistics after synthesis, including the estimated interconnect delays since this will be more useful for someone looking to implement the core. \$\endgroup\$
    – ks0ze
    Jul 18, 2016 at 20:04

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