Yes. It is conceivable that U2 will power up and operate normally, or that some units out of a large lot will do so. But it is much more likely that U2 will attempt to power up and get into a bad state.
There are a lot of ways to deal with this. One is to put an isolation buffer near U1, and power the isolation buffer from the output of U4 (the same LDO that powers U2). Isolation buffers are specifically designed to have high impedance at all inputs when VDD = 0V. One example is fairchild/onsemi part number NC7WZ17P6X.
Another way, if the hardware supports it, is to just make the IO signal into an open-collector signal, and pull it up to the output of U4. You would have to insure somehow that U1 never drives it high or enables an internal pullup.