Let's assume I'm talking about a typical single-antenna 5 GHz center-frequency 40 MHz bandwidth 802.11 receiver, but I'm interested more generally. What components in a wireless receiver draw the most power? And how do the power consumption of these components change as a function of bandwidth?
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1\$\begingroup\$ 802.11 is Wifi so a working device cannot be a receiver (RX) only. It must be a transceiver(RX/TX). Typically this transceiver is a single chip. So that chip would consume the most power as it is basically the only active component. Or do you mean, the blocks inside the chip ? Like in the receiver chain ? Usually the transmit is the most power hungry but not always. If there is also an application processor on the chip, that could be the most power hungry as well. There are no typical answers as much as there are no typical designs. \$\endgroup\$– BimpelrekkieAug 31, 2017 at 13:38
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\$\begingroup\$ In modern Wifi transceivers the channel bandwidth is mainly controlled in digital logic so changing the bandwidth will not change power consumption much. A higher datarate might require more from the digital baseband though so power consumption of that part might increase. \$\endgroup\$– BimpelrekkieAug 31, 2017 at 13:41
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\$\begingroup\$ Yes, I'm interested in comparing the power draw of the blocks inside the receive chain. For example, the ADC, amplifiers, mixers, filters, etc. \$\endgroup\$– awelkieAug 31, 2017 at 13:44
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\$\begingroup\$ Wouldn't changing the bandwidth change the sampling rate of the ADC? Would that cause a significant difference in the power consumption of the receive chain? \$\endgroup\$– awelkieAug 31, 2017 at 13:45
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1\$\begingroup\$ ADC sample rate it does not need to decrease (designing a fixed sample-rate ADC might be less work) and it might not even save that much power anyway since modern ADCs consume very little power. In my experience often the LNA usually consumes most power in RX since it needs gain and low noise. For low noise you want low impedance levels and for that some current is needed. Still, where the power is mostly used depends very much on the overall design. And unless you work for a company designing such ICs you will not get that information. \$\endgroup\$– BimpelrekkieAug 31, 2017 at 14:37
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MOSFETs need high current to achieve high transconductance and thus low random noise. Also, for low distortion, low 2nd order and low 3rd order distortion, achieved by designing for high intercept-points 2nd and 3rd, you need high currents. Thus that front end amplifier (LNA) is the hot spot.
However, if you are in a strong-signal location with low interfering tones in nearby channels and low out-of-band blocker energy, the Receiver control logic may measure the BitErrorRate or the residual errors during the initial adaptive-equalization time, and decide the LNA current can be reduced.
answered Aug 31, 2017 at 17:39