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schematic

simulate this circuit – Schematic created using CircuitLab

I created the above circuit. There is essentially a switch that is normally high. I press a button. Using a NTE4049T hex inverter, I create a low to high edge transition. This provides the clk input to a 74HCT175 D flip flop. Everything is run at TTL, 5 Volts. The output of the D flip flop is fed into another NTE4049T hex inverter to then feed the D input of the flip flop.

Ideally, when the button is pressed, I would create a toggle of the Q output line.

This does not happen. In fact, there is some oscillation at the signal output, but no finite transition of state.

I realize that this is a result of continuous toggling/bad design. How is this problem solved? If I chained the output of the D flip flop into another flip flop, also clocked to the same edge, to then generate an inverted output for the first flip flop, would that solve the state oscillations? Could I pass the output through a series of buffers to create a time delay?

The first pic is the waveform of the switch with the rc network. There is an instaneous drop when the switch is depressed. This drop, through an inverter, is what causes my clk signal to go high.

The pictures below show a high level view of the Q signal output as well as a zoomed in image at the tail where the Q signal then goes back low. I believe in this tail section the capacitor is charging. I'm not sure why it would cause the d flip flop to again trigger. There should not be a rising edge?

The light blue line represents the clock transition signal on the flip flop. The yellow line represents the D signal being fed into the flip flop. The dark blue line represents the Q signal of the flip flop, just before going into the inverter. The inverted output will again feed the flip flop a D.

How is a problem like this solved in practice if I cannot solve it in the above design? Thanks

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    \$\begingroup\$ Search for "switch debouncing" - mechanical switches don't switch cleanly, the contacts rattle around for a few ms. You can see that in your trace. Sort that first, and see what happens then :) \$\endgroup\$
    – awjlogan
    Dec 13, 2018 at 15:42
  • \$\begingroup\$ Change your inverters into Schmitt Trigger inverters. If 74LS04 for example, use 74LS14. Schmitt Triggers provide switch debouncing. \$\endgroup\$
    – StainlessSteelRat
    Dec 13, 2018 at 17:16
  • \$\begingroup\$ @StainlessSteelRat You still need an RC network - looking at Jeffrey's excellent traces (+1 for that), the bounces are deep enough to cause the output to change despite the extra margin hysteresis provides. A good link: pubweb.eng.utah.edu/~cs5780/debouncing.pdf \$\endgroup\$
    – awjlogan
    Dec 13, 2018 at 17:24
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    \$\begingroup\$ I actually did have a capacitor in the circuit as an RC network. It was not shown in the above pic. I will edit and post a pic of the triggered waveform from the switch press. The reason I did not include the cap in the diagram was that I thought it didn't matter in this version of my circuit test. With the cap, the fall in voltage from the switch press is instantaneous, then follows a gradual build of voltage over time (.3 sec or so) . The fall in voltage from the switch press, through an inverter is what creates my clock. \$\endgroup\$
    – Jeffrey Edward Messikian
    Dec 13, 2018 at 19:15
  • \$\begingroup\$ Thanks for the edit - try reducing either the capacitor or resistor values by a factor of 10, the RC constant is probably too high so the input to the inverter is in an undefined region too long. \$\endgroup\$
    – awjlogan
    Dec 14, 2018 at 10:20

1 Answer 1

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To fill out the comments a little, the problem (I suspect) is that your debouncing RC circuit is incorrectly sized. With \$C=3.3\ \mu \mathrm{F}\$ and \$R = 100\ \mathrm{k}\Omega\$ gives a time constant of \$0.33\ \mathrm{s}\$. Your traces show that when you close the switch, you get a nice clean edge (as you'd expect). When you release the switch, the capcacitor starts to charge. Using the equation \$V_C = V_\mathrm{in}(1-e^{\frac{-t}{RC}})\$, you can rearrange to find \$t = -RC\ln(1-\frac{V_C}{V_\mathrm{in}})\$. Using the values of \$V_{IL} = 1\ V\$ (maximum logic LOW input) and \$V_{IH} = 4\ V\$ (minimum logic HIGH input) from the inverter's datasheet shows that the inverter's input is in an undefined state (\$V_{IL} < V_\mathrm{in} < V_{IH}\$) for about 460 ms. This is consistent with you seeing an extra transition at the midpoint of the trailing edge. Try reducing the value of either \$R\$ or \$C\$ by a factor of 10, and ideally also use a Schmitt trigger input inverter as suggested in the comments.

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  • \$\begingroup\$ Thank you. I will try what you say. I did calculate .33 as well as about 5RC (1.65) to charge cap-which is probably waay too long. I will reduce values and get a schmit trigger inverter. \$\endgroup\$
    – Jeffrey Edward Messikian
    Dec 14, 2018 at 14:24

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