VHDL: Convert std_logic to std_logic_vector

Question

I'm trying to make a 4 bit adder with carry in & out, but I am having trouble converting Cin (Carry-in) to the type std_logic_vector when summing Sum and Cin together below in the architecture. Do you have any idea how i can make these types fit so that I can perform arithmetic on them together?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity four_bit_adder_simple is
        port(
                A, B : in std_logic_vector(3 downto 0);
                Cin : in std_logic;
                Sum : out std_logic_vector(3 downto 0);
                Cout : out std_logic);
end four_bit_adder_simple;

architecture unsigned_impl of four_bit_adder_simple is
    signal total : std_logic_vector(4 downto 0);
begin
        Sum <= std_logic_vector(resize(unsigned(A),5) + resize(unsigned(B),5));
        total <= Sum + Cin;
        Cout <= total(4);
end unsigned_impl;

EDIT: It was an error that I made Cout a 2 bit std_logic_vector. It should just have been a simple std_logic.

Answer 1

You need to cast cin to an unsigned, then add it in.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity four_bit_adder_simple is
    Port ( a    : in  std_logic_vector(3 downto 0);
           b    : in  std_logic_vector(3 downto 0);
           cin  : in  std_logic;
           sum  : out std_logic_vector (3 downto 0);
           cout : out std_logic );
end four_bit_adder_simple;

architecture Behavioral of four_bit_adder_simple is
    signal total : std_logic_vector(4 downto 0);
begin

    total <= std_logic_vector(resize(unsigned(a),5) + resize(unsigned(b),5) + unsigned'('0'&cin));
    sum   <= total(3 downto 0);
    cout  <= total(4);

end Behavioral;

You'll end up with this:

Note that resize returns an unsigned here.

Answer 2

Seeing as to how the question was not actually answered:

signal s_vector: std_logic_vector(0 downto 0);
signal s_bit   : std_logic : = '1';
...
s_vector <= (0 => s_bit);

Answer 3

The following is a simplification of your design that meets all the requirements and compiles in VHDL-93 onwards. It uses std_logic_unsigned rather than numeric_std. (Forgive the style changes, automatic when I typed and tested it.)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity FOUR_BIT_ADDER_SIMPLE is
  port(
    A                             : in  std_logic_vector( 3 downto  0);
    B                             : in  std_logic_vector( 3 downto  0);
    C_IN                          : in  std_logic;
    SUM                           : out std_logic_vector( 3 downto  0);
    C_OUT                         : out std_logic
  );
end FOUR_BIT_ADDER_SIMPLE;


architecture RTL of FOUR_BIT_ADDER_SIMPLE is

  signal total                    : std_logic_vector( 4 downto  0);

begin

  total  <=  ('0' & A) + ('0' & B) + ("0000" & C_IN);

  SUM    <=  total( 3 downto  0);
  C_OUT  <=  total( 4);

end architecture RTL;

The 5-bit addition is done in one line by first padding each element with leading zeroes.