Why does the clk not appear on the device under test?

Question

The clk signal is not being provided to the device under test from the test bench. I am unable to find the issue. It simply outputs 'U'.

What could be the issue?

The current output

Testbench for counterEx

library ieee; 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counterEx_tb is
end counterEx_tb;

architecture arch of counterEx_tb is
    constant M : integer := 10;
    constant N : integer := 4;
    constant T : time := 20 ns; 

    signal clk, reset : std_logic;  -- input
begin

    unit : entity work.counterEx
        generic map (M => M, N => N)
        port map (clk=>clk, reset=>reset);

    -- continuous clock
    process 
    begin
        clk <= '0';
        wait for T/2;
        clk <= '1';
        wait for T/2;
    end process;


    -- reset = 1 for first clock cycle and then 0
    reset <= '1', '0' after T/2;

end arch;

counterEx (device under test code)

library ieee; 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counterEx is 
generic( 
    M : natural := 6;
    N : natural := 4 -- N bits are required for M
    );
port(
    clk, reset : in std_logic
);
end entity; 

architecture arch of counterEx is 
    type stateType_moore is (start_moore, count_moore);
    signal state_moore_reg, state_moore_next : stateType_moore;
    signal count_moore_reg, count_moore_next : unsigned(N-1 downto 0);
begin 
    process(clk, reset)
    begin
        if reset = '1' then
            state_moore_reg <= start_moore;
            count_moore_reg <= (others => '0');
        elsif rising_edge(clk) then
            state_moore_reg <= state_moore_next;
            count_moore_reg <= count_moore_next;
        end if; 
    end process;
    
    process(count_moore_reg, state_moore_reg)
    begin 
        case state_moore_reg is
            when start_moore =>
                count_moore_next <= (others => '0');
                state_moore_next <= count_moore;
            when count_moore =>
                count_moore_next <= count_moore_reg  + 1;
                if (count_moore_reg  + 1) = M - 1 then
                    state_moore_next <= start_moore;
                else
                    state_moore_next <= count_moore;
                end if;
        end case;
    end process; 

    --out_moore <= std_logic_vector(count_moore_reg);
end arch; 

Answer 1

I modified the testbench by declaring the component, instantiating the DUT properly, used std.env.stop(0) and simulated the design long enough. Now it works fine!

You need to simulate your design long enough to see the output.

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity counterEx_tb is
end counterEx_tb;

architecture arch of counterEx_tb is
   
component counterEx is 
generic( 
    M : natural := 6;
    N : natural := 4 -- N bits are required for M
    );
port(
    clk, reset : in std_logic
);
end component counterEx; 
   constant M : integer := 10;
   constant N : integer := 4;
   constant T : time := 20 ns; 

   signal clk, reset : std_logic;  -- input
begin

    unit : counterEx
        generic map (M => M, N => N)
        port map (clk=>clk, reset=>reset);

    -- continuous clock
    clock_proc: process 
    begin
        clk <= '1';
        wait for T/2;
        clk <= '0';
        wait for T/2;
    end process clock_proc;


    -- reset = 1 for first clock cycle and then 0
    stim_proc: process
    begin
    reset <= '1', '0' after T/2;
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    std.env.stop(0);
    end process stim_proc;
end arch;