P-channel MOSFET inrush current limiting

Question

I have been searching EESE and Google for several weeks now for a solution to this problem, and while I found some proposals that seemed promising, the real-world implementation fell short of expectations.

I have a voltage regulator on a board with 10 μF input capacitance to help protect against brownout conditions. I have a fuse in series with the power supply sized to 125 mA for various reasons, and just to be clear, I have not found any slow-blow versions that meet my requirements. The power supply can be anything from 5 volts to 15 volts DC, most likely a lead-acid battery. When the battery is first connected I see an inrush current with a peak of approximately 8 amps over 8 μs, which very quickly blows the 125 mA fuse. Okay, so I need to limit the inrush current. No big deal, right?

I tried a number of different options, but this is the one that seemed most promising:

R1 and R2 form a voltage divider that limits the Vgs to prevent damage to the MOSFET, and along with the capacitor form an RC delay that allows the FET Vgs to increase more slowly, keeping the FET in its ohmic region for a longer amount of time. Makes perfect sense. Higher capacitance = slower turn-on = less inrush current.

Well that's all fine and dandy, except that after increasing the capacitor from 1 μF to 4.7 μF to 10 μF, I realized I bottomed out at an inrush current of around 1.5 Apk over 2 μs. After reaching that point, no matter what capacitance I added for C1 (I tried up to 47 μF) the inrush current wouldn't drop any lower than 1.5 Apk. Obviously this current was still much too high and would blow my fuse in an instant. I can't increase the current rating of the fuse, so I need to find a way to make this work.

My current hypothesis is this:

Cgs and Cgd are the intrinsic gate-source and gate-drain capacitances of the MOSFET, and while they are relatively very small (50 pF-700 pF), my theory is that they are acting as a pass-through when Vin is first applied. Since these capacitances can't be reduced, they (especially Cgd) are the limiting factors that prevent me from lowering the inrush current below 1.5 Apk.

What other options are there for limiting inrush current? I have found various one-chip solutions for hot-swap applications, but they have a similar topology to the above circuit and I imagine they would have similar drawbacks.

Vin can be as low as 5 volts, so if I take into account reverse polarity protection provided by a Schottky diode, the voltage drop across the fuse, the drop across the MOSFET on-resistance, and drops due to the cable (can be fairly long) connecting this board to the supply, my voltage drop is becoming fairly significant (the voltage regulator this is feeding into requires roughly 4.1 V in order to regulate properly). A series current limiting resistor is unfortunately not going to be an option.

The other restriction I have is space. I have approximately 4.5 x 4.5 square millimeters to work with. The above circuit was just barely going to fit, so adding even more components is not really an option. Otherwise this would have been a slightly easier problem to solve.

Answer 1

You have sortof the right idea:

But the capacitor is in the wrong place. For slew rate control, it should be between the drain and the gate, not the source and the gate as you show it. Putting it between drain and gate causes feedback so that when the drain rises quickly, it turns the FET off more.

Just a cap between drain and source can be good enough. The timing relies on some parameters that are usually poorly known, and the slope limiting doesn't kick in until the gate gets to near its threshold voltage.

Here is a more sophisticated slope-limiting power input circuit I've used a few times.

This device connects to the rest of the system via two CAN bus lines, ground, and 24 V power. It can be hot-plugged at any time. It can't be allowed to suddenly draw a large pulse of current when plugged in.

CANPWR is the direct connection to the 24 V power bus, and 24V is the is the internal 24 V power in this device. The purpose of this circuit is to make 24V rise slowly enough to limit the inrush current to a acceptable level. After that, it should get out of the way as much as possible.

A rising voltage slope on 24V causes current thru C2, which turns on Q3, which turns on Q1, which tries to turn off the gate drive to Q2, the power pass element. Note that this kicks in with less than 1 V on 24V.

Slope limiting feedback occurs when there is enough voltage across R4 to turn on Q3. Figure that's about 1.5 V, considering the drop across R5 required to turn on Q1. The slope limit is therefore what it takes to pass (1.5 V)/(10 kΩ) = 150 µA thru C2. (150 µA)/(1 µF) = 150 V/s. To rise 24 V should therefore take about 150 ms. I remember measuring a few 100 ms of rise time with a scope, so that all checks out.

Once the 24V net has risen, R3 holds Q2 on, and D2 keeps its gate-source voltage within the allowable range.

Answer 2

Low tech solutions:

• Mount the fuse AFTER the input cap. Add a 100nF cap at regulator input to ensure its stability.
• Replace fuse with Polyswitch (which will have a slower reaction time).
• Put capacitor in parallel with Fuse

My preferred solution would be the first or second one.

Medium tech solution:

Add a resistor in series with the input cap in parallel with a schottky diode. The resistor will slow down the capacitor charge, and the diode will allow quick discharge if LDO needs current. Bit of a wonky solution...

High tech solution: Current limiter using...

• a Depletion MOSFET like DN2540.
• current-limited high-side load switch

Answer 3

Any practical logic based "supervisory" circuit will not fit in the space you have available. A simple NTC resistor would probably end up being too large as well. certainly look into those though, maybe there's a tiny one that fits your purpose.

If you had more space I'd use a constant-current limiter which chops the output, kind of like current PWM, until the cap is charged. Use a sense resistor, comparator, and another PFET before the caps. But this will absolutely not fit in your circuit. You COULD design the module I described as an in-line device before it gets to the VIN of your circuit, from the battery. Same goes with the NTC resistor, could be something before the PCB with your circuit shown.

The better, discrete solution might be this: A 2 ohm power resistor in series before your capacitors/FET is definitely still an option. If you have a fuse rated at 125mA, you obviously have a very low power load in normal conditions. To make allowance for the voltage headroom, you should instead of using a schottky diode, use a reversed PFET (the drain-source would be opposite the normal configuration for a high-side switch), with the base grounded. This is an extremely low V-forward solution to reverse polarity protection. 2 Ohms at your 125mA rated fuse current (a bad idea to operate that close to the holding current btw) will only lose you 250mV, less than your Schottky was going to lose, and still plenty of room for cable and PFET drop. On resistance for the PFETs will be in the order of 30-90 milliohms if you get the good ones. The best you can do is prototype the circuit, and test it. A resistor and a reversed PFET should not take up much room at all! in 4.5mm x 4.5mm you could fit a SOT23 (or SC-70) package PFET and a 0.25W 0805 package resistor I think.

A FET like this MTM231232LBF would work great, but it needs a zener diode clamp on the gate to ground after the device. see image below for example circuit, but the Zener voltage needs to be obviously <10V to protect the gate. A zener voltage between 5-7V would work.

The zener and resistor combo can be the smallest possible packages you can find. They hardly do anything except ensure your FET doesn't pop.

So a combination of the series resistor, and a PFET-based polarity protection to give you the voltage headroom you need, will help avoid the appearance of a short circuit from your capacitors down-stream at the load. The MOSFET itself doesn't turn on instantly either, so it acts as a bit of a current-limiter just in its non-linear turn-on behaviour.

Answer 4

I'm trying to do something similar and this Application Note has pretty precise directions on how to lay out your circuit as well as calculating the appropriate values: http://www.onsemi.com/pub/Collateral/AND9093-D.PDF

^{simulate this circuit – Schematic created using CircuitLab}

Answer 5

Note AND9093 is referenced for load switches so in your schematic without the extra Fet pulling the gate to ground you will instantly turn on and will not hold the inrush current in check. The values you calculate from AND9093 should be very close but you need to add an extra cap from the source to gate so at turn on the gate is pulled up for just a bit to allow the extra gate to drain capacitance to hold the Mosfet in the linear region as needed to keep the current down.

Try this circuit below which i have used in the past and it will work as needed. Simulate it and you will also see that it works very well also. Make sure you use the right parameters form the Fet data sheet to get your values in the ball park.

Answer 6

I know this is an old item and my answer is not fully answering the OP's question. However variouse different google searches pointed on inrush current limiting pointed to this item, so I thought to add my result as an answer for others

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While searching for a similar solution and none of the above ones satisfied my timing requirements (big capacitive load -> long inrush limit time).

Also if using small resistors and capacitors (e.g. 0402 or 0603) the footprint exceeding the Mosfet size should be limited.

For huge capacitive loads and more flexible timing requirements, this is a more sophisticated solution, which is difficult to achieve with just a Drain-Gate capacitor circuit.

^{simulate this circuit – Schematic created using CircuitLab}

Details about this circuit and how to calculated the values is given here

Answer 7

The circuit below uses C1 to sample the slew rate on CLOAD, and uses that to control the pass element M1.

^{simulate this circuit – Schematic created using CircuitLab}

I have something similar in another answer of mine and I'd link it if I could find said answer to start with. Sorry about that.