update: I will rewrite my whole VHDL-Statemachine because I had just trouble with the basics of FSM. I will try to find a easier FSM for this.
I have a state machine and as I really forced to use a state machine I maybe didn't check some LATCH issues you discovered.
This results in:
In one state I have a counter which should only increment by 1. But:
My counter increments by 2. Why?
How is that possible?
My Code Ressources:
Here is my checker-module:
https://paste.ofcode.org/DrbFJc78h84dRFz7DvVGXQ
Here is my generator-module:
https://paste.ofcode.org/xhkssfnbBukhQyM7QcpqMj
Here is the dedicated crc calculator:
https://paste.ofcode.org/ALUBzZCUrvTcdVRmKGnv5U
Here is my testbench you asked for:
https://paste.ofcode.org/354Lk9k7NTNk75NXrN9ymSw
I want that it only increases by one if
- my crc was right ( my axi checker checks all incoming frame data and calculates the crc, then it compares it with the last 4 Bytes of the Frame [which is also a crc].)
- it is in the state data check
This simulation-foto shows my problem:
signal identic_crc_in_frame_cnt : std_logic_vector (10 downto 0 ):= (others => '0');
I tried another counter, and now it always adds 4.
signal testcnt : unsigned (3 downto 0):= X"0";
testcnt <= testcnt +2 ;
I have a sync method....
SYNC_PROC2 : PROCESS (axi_reset, m_axis_clk, m_axis_tkeep, m_axis_tvalid, m_axis_tlast)
BEGIN
IF rising_edge(m_axis_clk) THEN
IF (axi_reset = '1') THEN
-- reset..
current_state <= IDLE;
--received_frame_cnt <= (others => '0');
ELSE
-- normal mode
current_state <= next_state;
IF (current_state = CHECK_ADR1) THEN
column_data_correct_cnt <= (OTHERS => '0');
ELSE
END IF;
And this would be a part of the case
WHEN CHECK_DATA =>
--- Check tdata only if tvalid = 1 , because tvalid means MAC wants to send valid data
IF (m_axis_tvalid = '0') THEN
IF (m_axis_tlast = '1') THEN
next_state <= CHECK_ADR1;
-- do this maybe somewhere else:
crc_calc_enabled <= '0';
if ( m_axis_tdata(31 downto 0) = prev_prev_CRC_REG_tb(31 downto 0)) then
crc_ok <= '1';
error_flag_crc <= '0';
identic_crc_in_frame_cnt <= identic_crc_in_frame_cnt + '1';
testcnt <= testcnt +3 ;
else
crc_ok <= '0';
error_flag_crc <= '1';
end if;
After the code below it should go to next state...
IF (m_axis_tlast = '1') THEN
next_state <= CHECK_ADR1;
I changed SYNC_PROC to (like u said)
SYNC_PROC2 : PROCESS ( m_axis_clk)
BEGIN
IF rising_edge(m_axis_clk) THEN
-- AXI pattern Checker
my_axi_checker : AXI_CHECKER port map (
m_axis_tkeep => tkeep,
m_axis_tvalid => tvalid,
m_axis_tdata => taxi_data_tb,
m_axis_tready => open, -- not needed
m_axis_clk => m_axis_clk,
axi_start => start,
axi_reset => axi_reset,
m_axis_tlast => tlast
);
--- start the axi interface tb
axi_reset <= '0' after 10 ns;
start <= '1' after 12 ns; -- Starts an axi_stream transaction
--
-- axi_data (63 downto 0)<= axi_data_content(63 downto 0); -- axi data
-- m_axis_tdata <= std_logic_vector(axi_data); -- data is converted to std logic vector and layed onto signal!
-- generates testbench clock:
axiclk : process
begin
wait for 10 ns;
m_axis_clk <= '0';
wait for 10 ns;
m_axis_clk <= '1';
end process axiclk;
On this picture you can see tlast and the testebnch clk and the two counters...( increment should be like in the code - anyway, its always double xD)
After I updated my code it gets stranger :D