Synthesis Result : RTL vs Technology Map Viewer - Electrical Engineering Stack Exchange most recent 30 from electronics.stackexchange.com 2019-09-16T04:18:36Z https://electronics.stackexchange.com/feeds/question/353755 https://creativecommons.org/licenses/by-sa/4.0/rdf https://electronics.stackexchange.com/q/353755 3 Synthesis Result : RTL vs Technology Map Viewer Codelearner777 https://electronics.stackexchange.com/users/155987 2018-02-02T23:04:22Z 2018-02-03T08:48:54Z <p>I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something?</p> <p>this is the truth table</p> <pre><code> RTL Technology Map A (NOT A) p_a ((A XOR p_a) AND A) ((NOT A) AND p_a) 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 </code></pre> <p><a href="https://i.stack.imgur.com/5oMx1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5oMx1.png" alt="enter image description here"></a></p> <pre><code>library ieee; use ieee.std_logic_1164.all; entity keypad is port ( clk : in std_logic; rst : in std_logic; a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; e : in std_logic; keypad : out std_logic_vector (4 downto 0) ); end entity keypad; architecture rtl of keypad is signal p_a, p_b, p_c, p_d, p_e : std_logic; BEGIN KEY: process(A, B, C, D, E, rst, clk) begin if rst = '1' then p_a &lt;= '0'; p_b &lt;= '0'; p_c &lt;= '0'; p_d &lt;= '0'; p_e &lt;= '0'; elsif clk'event AND clk='1' then p_a &lt;= A; p_b &lt;= B; p_c &lt;= C; p_d &lt;= D; p_e &lt;= E; end if; end process; keypad(4) &lt;= '1' when a /= p_a and a = '1' else '0'; keypad(3) &lt;= (B XOR p_b) AND B; END architecture; </code></pre> <p>I appreciate any suggestion.</p> https://electronics.stackexchange.com/questions/353755/-/353756#353756 0 Answer by Oldfart for Synthesis Result : RTL vs Technology Map Viewer Oldfart https://electronics.stackexchange.com/users/169836 2018-02-02T23:12:27Z 2018-02-02T23:12:27Z <p>The Logic mapper uses "functional" symbols, which is just a square with what function that block fulfills. This can map onto all kinds of logic.</p> <p>For example if you use a '+' the function will be 'adder': a square with two inputs and an output. Which maps on a numerous gates. It can also be mapped on different gates e.g. a slow ripple carry adder or a faster carry-look ahead adder. </p> <p>I also allows a tool to work with a mixture of e.g. Verilog and VHDL. They use two compilers to map the language on functional primitives and then they can use one tool to go to gates and optimize. </p> <p>And they can use a different tool to go to gates and optimize for a totally different FPGA type. </p> https://electronics.stackexchange.com/questions/353755/-/353757#353757 2 Answer by C_Elegans for Synthesis Result : RTL vs Technology Map Viewer C_Elegans https://electronics.stackexchange.com/users/58084 2018-02-02T23:16:18Z 2018-02-02T23:16:18Z <p>They are equivalent. The code/rtl-viewer give the equation as (B xor p_b) and B and the technology map view shows it as B and !p_b. The former can be simplified to the latter as follows</p> <p>\$(A \oplus B)A \$</p> <p>\$(A\bar{B} + \bar{A}B)B\$</p> <p>\$AA\bar{B} + A\bar{A}B\$</p> <p>\$A\bar{B} + 0\$ (\$A\bar{A}\$ is 0, so the right side is 0)</p> <p>\$A\bar{B}\$</p> https://electronics.stackexchange.com/questions/353755/-/353796#353796 2 Answer by Mitu Raj for Synthesis Result : RTL vs Technology Map Viewer Mitu Raj https://electronics.stackexchange.com/users/166884 2018-02-03T06:29:36Z 2018-02-03T06:29:36Z <p>Both are equivalent. RTL viewer shows what digital logic is implemented by your HDL code. It would be what you draw on a paper, if you were to design a digital circuit that satisfy your functional requirement. Technology viewer shows how this digital circuit is implemented inside FPGA. It depends on the technology inside FPGA. For eg. An OR gate is implemented as a simple LTU inside FPGA. It shows how LUTs are used , which IOBs it has used, whether it is using buffers on lines, etc.</p> <p>In your technology viewer, it shows that the combination logic produced by two logic gates is implemented as a single truth table in an LUT inside FPGA. Just as C_elegants has answered.</p> https://electronics.stackexchange.com/questions/353755/-/353808#353808 1 Answer by Tom Carpenter for Synthesis Result : RTL vs Technology Map Viewer Tom Carpenter https://electronics.stackexchange.com/users/53368 2018-02-03T08:42:47Z 2018-02-03T08:48:54Z <p>You'll find this a lot when using the graphical netlist viewers. The compiler does clever things you may not expect, and which aren't always immediately obvious.</p> <p>The reason is because the combinational logic cell has inverting inputs in your example. You need to check both the contents (F) and the comb cell itself in the properties view:</p> <p>Then the contents:</p> <p><a href="https://i.stack.imgur.com/fOyJ9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fOyJ9.png" alt="Contents of Cell"></a></p> <p>The comb cell:</p> <p><a href="https://i.stack.imgur.com/mHxgz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/mHxgz.png" alt="Inverted Inputs"></a></p> <p>There are your missing inverters. The combinational cell as "Active Low" inputs, so the internal logic has to invert them.</p> <p>You can look at the equation view to confirm:</p> <p><a href="https://i.stack.imgur.com/hcudc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hcudc.png" alt="Equation View"></a></p> <p>Here we see the equation becomes:</p> <p>$$\overline{p\_a} \cdot a$$</p>