FPGA Max PWM Frequency - Electrical Engineering Stack Exchange most recent 30 from electronics.stackexchange.com 2019-07-20T11:44:50Z https://electronics.stackexchange.com/feeds/question/430474 http://www.creativecommons.org/licenses/by-sa/3.0/rdf https://electronics.stackexchange.com/q/430474 1 FPGA Max PWM Frequency Damien https://electronics.stackexchange.com/users/140844 2019-04-03T09:40:49Z 2019-04-03T14:35:31Z <p>Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps".</p> <p>Being new in FPGA, I quite could not quite figure out how to extract this information from the datasheet.</p> <p>Let's take <a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf" rel="nofollow noreferrer">ICE40LP384-SG32</a> as an example. </p> <p>There are several pages concerning timings, but I am not sure what is relevant in this context and how the final max PWM frequency can be calculated.</p> <p>Maximum sysIO Buffer Performance states a speed of 250 MHz.</p> <p>With a clock frequency of 250 MHz, and a PWM counter of 2'000 steps that would yield a 125 kHz max PWM output frequency, is this correct or is there more timing consideration involved?</p> <p>Could it be clocked faster than that? What is the relevant information there?</p> https://electronics.stackexchange.com/questions/430474/-/430505#430505 4 Answer by Dave Tweed for FPGA Max PWM Frequency Dave Tweed https://electronics.stackexchange.com/users/11683 2019-04-03T12:26:01Z 2019-04-03T12:26:01Z <p>If you just want to produce a PWM signal, most modern FPGAs have high-speed SERDES (serialize/deserialize) circuits built into their I/O that can run at tens of GHz. 10 GHz/2000 = 5 MHz PWM.</p> <p>But often, PWM is just being used as a crude form of DAC. It's simple, but has severe bandwidth limitations. If that's what you're doing, other techniques such as delta-sigma modulation give you better tradeoffs.</p> https://electronics.stackexchange.com/questions/430474/-/430527#430527 1 Answer by Elliot Alderson for FPGA Max PWM Frequency Elliot Alderson https://electronics.stackexchange.com/users/189585 2019-04-03T14:18:49Z 2019-04-03T14:18:49Z <p>Your are essentially correct. When generating PWM (or any periodic waveform) using counters, one limit for the <strong>maximum possible frequency</strong> will be equal to the input clock frequency divided by the maximum value of the counter.</p> <p>In practice there may be other factors that limit the maximum frequency, such as the maximum frequency of an output pin. It is more likely that you would be limited by the ability of the logic to generate the PWM waveform. Your counter must have some kind of logic block that calculates <code>count+1</code> as the next value in the counter. To control the duty factor you need another register that holds some value, and comparison logic to detect when the counter equals the register value (to toggle the output pin).</p>