7 Removed capital title and corrected typos
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HELP WITH Help needed with SPARTAN-3AN FPGA FREQUENCY DOUBLER REGADING-THANKS FOR ALL TO READ THISfrequency doubler

Here iI attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked outputs are not providing any output in SPARTAN FPGA development board (https://www.pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an) there is an output LED'S are assigned for clk0,locked,clk2x pins (p7,p8,p10 in datasheet) are output ,pins and (p57(clk),p18(rst)) are input pins.but, i got an output only at the clk0(p7) that is 2.5 Mhz same as clk50(intenaly generated clock from 50Mhz of input clock)

enter image description here

module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

input clk; input rst; output clk0;
output clk2x; output locked;

reg clk50=0; wire clk0; wire clk2x; wire locked;

reg [7:0] count=0;

clkdcm_test instance_name ( .CLKIN_IN(clk50), .RST_IN(rst), .CLK0_OUT(clk0), .CLK2X_OUT(clk2x), .LOCKED_OUT(locked) );

always @(posedge clk) //---2.5 Mhz signal from 50 MHZ crystal oscillator begin count<=count+1;

if(count<=9) clk50<=1; if(count>=10) clk50<=0; if(count>=19) count<=0; end endmodule

//----------

PlanAhead Generated physical constraints

NET "clk" LOC = P57; NET "clk0" LOC = P7; TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%; NET "clk2x" LOC = P8; NET "locked" LOC = P10; NET "rst" LOC = P18;

module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

input clk;
input rst;
output clk0;  
output clk2x;
output locked;

reg clk50=0;
wire clk0;
wire clk2x;
wire locked;

reg [7:0] count=0;

clkdcm_test instance_name (
    .CLKIN_IN(clk50), 
    .RST_IN(rst), 
    .CLK0_OUT(clk0), 
    .CLK2X_OUT(clk2x), 
    .LOCKED_OUT(locked)
    );

always @(posedge clk) //---2.5 Mhz signal from 50 MHZ crystal oscillator 
begin 
     count<=count+1;

  if(count<=9) 
     clk50<=1;
  if(count>=10)
     clk50<=0;
  if(count>=19)
     count<=0;
end
endmodule



//----------

# PlanAhead Generated physical constraints 

NET "clk" LOC = P57;
NET "clk0" LOC = P7;
TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%;
NET "clk2x" LOC = P8;
NET "locked" LOC = P10;
NET "rst" LOC = P18;

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HELP WITH SPARTAN-3AN FPGA FREQUENCY DOUBLER REGADING-THANKS FOR ALL TO READ THIS

Here i attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked outputs are not providing any output in SPARTAN FPGA development board (https://www.pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an) there is an output LED'S are assigned for clk0,locked,clk2x pins (p7,p8,p10 in datasheet) are output ,pins and (p57(clk),p18(rst)) are input pins.but, i got an output only at the clk0(p7) that is 2.5 Mhz same as clk50(intenaly generated clock from 50Mhz of input clock)

enter image description here

module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

input clk; input rst; output clk0;
output clk2x; output locked;

reg clk50=0; wire clk0; wire clk2x; wire locked;

reg [7:0] count=0;

clkdcm_test instance_name ( .CLKIN_IN(clk50), .RST_IN(rst), .CLK0_OUT(clk0), .CLK2X_OUT(clk2x), .LOCKED_OUT(locked) );

always @(posedge clk) //---2.5 Mhz signal from 50 MHZ crystal oscillator begin count<=count+1;

if(count<=9) clk50<=1; if(count>=10) clk50<=0; if(count>=19) count<=0; end endmodule

//----------

PlanAhead Generated physical constraints

NET "clk" LOC = P57; NET "clk0" LOC = P7; TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%; NET "clk2x" LOC = P8; NET "locked" LOC = P10; NET "rst" LOC = P18;

enter image description here enter image description here

enter image description here

enter image description here

enter image description here

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked outputs are not providing any output in SPARTAN FPGA development board (https://www.pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an) there is an output LED'S are assigned for clk0,locked,clk2x pins (p7,p8,p10 in datasheet) are output ,pins and (p57(clk),p18(rst)) are input pins.but, i got an output only at the clk0(p7) that is 2.5 Mhz same as clk50(intenaly generated clock from 50Mhz of input clock)

enter image description here

module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

input clk;
input rst;
output clk0;  
output clk2x;
output locked;

reg clk50=0;
wire clk0;
wire clk2x;
wire locked;

reg [7:0] count=0;

clkdcm_test instance_name (
    .CLKIN_IN(clk50), 
    .RST_IN(rst), 
    .CLK0_OUT(clk0), 
    .CLK2X_OUT(clk2x), 
    .LOCKED_OUT(locked)
    );

always @(posedge clk) //---2.5 Mhz signal from 50 MHZ crystal oscillator 
begin 
     count<=count+1;

  if(count<=9) 
     clk50<=1;
  if(count>=10)
     clk50<=0;
  if(count>=19)
     count<=0;
end
endmodule



//----------

# PlanAhead Generated physical constraints 

NET "clk" LOC = P57;
NET "clk0" LOC = P7;
TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%;
NET "clk2x" LOC = P8;
NET "locked" LOC = P10;
NET "rst" LOC = P18;

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6 deleted 398 characters in body; edited title
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Help with HELP WITH SPARTAN-3AN implementation errorFPGA FREQUENCY DOUBLER REGADING-THANKS FOR ALL TO READ THIS

While I was implementingHere i attached the routed nets for this program below into theverilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked outputs are not providing any output in SPARTAN FPGA development board (SPARTAN-3ANhttps://www.pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an) there is an output LED'S are assigned for clk0, Ilocked,clk2x pins (p7,p8,p10 in datasheet) are output ,pins and (p57(clk),p18(rst)) are input pins.but, i got an output only at the following error messageclk0(p7) that is 2.5 Mhz same as clk50(intenaly generated clock from 50Mhz of input clock) Can anybody help me find the mistakes in this module?

module DCMPLL(CLKIN_IN,RST_IN,CLKDV_OUT,CLK0_OUT,CLK2X_OUT,CLK90_OUT,LOCKED_OUT,STATUS_OUT);

input   CLKIN_IN;
input   RST_IN;
output  CLKDV_OUT;
output  CLK0_OUT;
output  CLK2X_OUT;
output  CLK90_OUT; 
output  LOCKED_OUT;
output  STATUS_OUT;


DCM_PLL instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .RST_IN(RST_IN), 
    .CLKDV_OUT(CLKDV_OUT), 
    .CLKIN_IBUFG_OUT(), 
    .CLK0_OUT(CLK0_OUT),  
    .CLK2X_OUT(CLK2X_OUT), 
    .CLK90_OUT(CLK90_OUT), 
    .LOCKED_OUT(LOCKED_OUT), 
    .STATUS_OUT(STATUS_OUT)
    );
endmodule

enter image description here


 

module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
   site pair.  The clock component <instance_name/DCM_SP_INST> is placed at site <DCM_X0Y0>.  The clock IO/DCM site can
   be paired if they are placed/locked in the same quadrant.  The IO component <CLKIN_IN> is placed at site <PAD53>. 
   This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is
   acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may
   lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf
   file to override this clock rule.
   < NET "CLKIN_IN" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "instance_name/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE

input clk; input rst; output clk0;
output clk2x; output locked;

The image below describes the instantiation of DCM for SPARTANreg clk50=0; wire clk0; wire clk2x; wire locked;

reg [7:0] count=0;

clkdcm_test instance_name ( .CLKIN_IN(clk50), .RST_IN(rst), .CLK0_OUT(clk0), .CLK2X_OUT(clk2x), .LOCKED_OUT(locked) );

always @(posedge clk) //-3AN using ISE 12--2.3:5 Mhz signal from 50 MHZ crystal oscillator begin count<=count+1;

screenshot if(count<=9) clk50<=1; if(count>=10) clk50<=0; if(count>=19) count<=0; end endmodule

//----------

PlanAhead Generated physical constraints

NET "clk" LOC = P57; NET "clk0" LOC = P7; TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%; NET "clk2x" LOC = P8; NET "locked" LOC = P10; NET "rst" LOC = P18;

enter image description here enter image description here

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Help with SPARTAN-3AN implementation error

While I was implementing this program below into the FPGA (SPARTAN-3AN), I got the following error message. Can anybody help me find the mistakes in this module?

module DCMPLL(CLKIN_IN,RST_IN,CLKDV_OUT,CLK0_OUT,CLK2X_OUT,CLK90_OUT,LOCKED_OUT,STATUS_OUT);

input   CLKIN_IN;
input   RST_IN;
output  CLKDV_OUT;
output  CLK0_OUT;
output  CLK2X_OUT;
output  CLK90_OUT; 
output  LOCKED_OUT;
output  STATUS_OUT;


DCM_PLL instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .RST_IN(RST_IN), 
    .CLKDV_OUT(CLKDV_OUT), 
    .CLKIN_IBUFG_OUT(), 
    .CLK0_OUT(CLK0_OUT),  
    .CLK2X_OUT(CLK2X_OUT), 
    .CLK90_OUT(CLK90_OUT), 
    .LOCKED_OUT(LOCKED_OUT), 
    .STATUS_OUT(STATUS_OUT)
    );
endmodule

 
ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
   site pair.  The clock component <instance_name/DCM_SP_INST> is placed at site <DCM_X0Y0>.  The clock IO/DCM site can
   be paired if they are placed/locked in the same quadrant.  The IO component <CLKIN_IN> is placed at site <PAD53>. 
   This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is
   acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may
   lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf
   file to override this clock rule.
   < NET "CLKIN_IN" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "instance_name/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE

The image below describes the instantiation of DCM for SPARTAN-3AN using ISE 12.3:

screenshot

HELP WITH SPARTAN-3AN FPGA FREQUENCY DOUBLER REGADING-THANKS FOR ALL TO READ THIS

Here i attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked outputs are not providing any output in SPARTAN FPGA development board (https://www.pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an) there is an output LED'S are assigned for clk0,locked,clk2x pins (p7,p8,p10 in datasheet) are output ,pins and (p57(clk),p18(rst)) are input pins.but, i got an output only at the clk0(p7) that is 2.5 Mhz same as clk50(intenaly generated clock from 50Mhz of input clock)

enter image description here

module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

input clk; input rst; output clk0;
output clk2x; output locked;

reg clk50=0; wire clk0; wire clk2x; wire locked;

reg [7:0] count=0;

clkdcm_test instance_name ( .CLKIN_IN(clk50), .RST_IN(rst), .CLK0_OUT(clk0), .CLK2X_OUT(clk2x), .LOCKED_OUT(locked) );

always @(posedge clk) //---2.5 Mhz signal from 50 MHZ crystal oscillator begin count<=count+1;

if(count<=9) clk50<=1; if(count>=10) clk50<=0; if(count>=19) count<=0; end endmodule

//----------

PlanAhead Generated physical constraints

NET "clk" LOC = P57; NET "clk0" LOC = P7; TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%; NET "clk2x" LOC = P8; NET "locked" LOC = P10; NET "rst" LOC = P18;

enter image description here enter image description here

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5 Remove VHDL tag.
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4 Improved English further and fixed title.
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3 format listings, put image inline
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2 added 783 characters in body
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