Skip to main content
9 events
when toggle format what by license comment
Dec 23, 2016 at 17:00 comment added Nick Alexeev @Sergei Fixed the first comment. Should be consistent now.
Dec 23, 2016 at 16:58 comment added Sergei Gorbikov Nick, 10x for an extensive and swift response. In your first comment, you meant copper area while used "copper pour" as i got: "If there are multiple traces covered by a copper pour, then the copper pour will short them." I got it, some people pour copper on the top layer this way hoping to reduce crosstalk or EMI.
Dec 23, 2016 at 16:48 comment added Nick Alexeev @Sergei p.s. When I wrote this I didn't have OrCAD in front of me, so this is from memory. By the way, this nomenclature isn't universal across across various PCB design packages. For example, Altium has got Solid Region and Polygon Pour.
Dec 23, 2016 at 16:48 comment added Nick Alexeev @Sergei Copper pour isolates tracks that cross it. Copper pour may also be attached to a net. In that case, it will isolate all nets, except the one that it's attached to. Copper pour has got a more complex behavior. In my experience, copper pour is used more often than copper area. Here's an example of a copper pour in one of my previous questions. Notice how the copper pour had created an isolation gap around the resistors and traces.
Dec 23, 2016 at 16:47 comment added Nick Alexeev @Sergei Copper area is just a polygon filled with copper. If a copper area covers a trace, then it will paint over the trace. If there are multiple traces covered by a copper area, then the copper area will paint over all of them and short them.
Dec 23, 2016 at 16:12 comment added Sergei Gorbikov +1, Nick, what's the difference between copper area and copper pour? 10x.
Apr 1, 2014 at 22:36 comment added bitsmack Thanks Nick, @Andyaka. I got the answer from Cadence :) Please take a look!
Apr 1, 2014 at 7:31 comment added Andy aka That's how I'd do it - overlap stuff with copper.
Apr 1, 2014 at 2:00 history answered Nick Alexeev CC BY-SA 3.0