if you are building up a number in binary, the 'right hand' bit is the least significant, and the processes is usually counting 'up' the index, or 'bit position' which goes left towards the most significant bit. This of course is entirely related to the "endian-ness" of the system architecture - which determines if it's the 7th or the zero-th bit as most significant.

A psuedo code for the receiver in a shift register of a UART might be:

• Oh look, i detected a start bit!
• oh look here are more bits coming in which match by baud rate settings! (timeout hasnt occured, etc)
• for each bit, starting index 0, if bit is high, put a 1 into the shift register, else put a zero into the shift register
• after the x number of data bits (could be 8-10 data bits in a serial frame) process is finished, and set flag for microcontroller to read my receive data register!

All of this is followed of course by 1 or 2 stop bits, and then the data line is kept at whatever idle level (usually high?) until the next transmission is detected.

Same style of thinking is used for bit-banging by software serial - as the pin level changes, increase the bit index and set/reset the bit on a "received byte" variable. It's essentially based on endian-ness of the system (little or big endian) and the fact that programmers like to use 0-indexing and starting at the lower end of a variable. Hardware UART transmit shift registers usually shift data out "backwards" than what you expect, as you mentioned in your question.

if you are building up a number in binary, the 'right hand' bit is the least significant, and the processes is usually counting 'up' the index, or 'bit position' which goes left towards the most significant bit. This of course is entirely related to the "endian-ness" of the system architecture - which determines if it's the 7th or the zero-th bit as most significant.

A psuedo code for the receiver in a shift register of a UART might be:

• Oh look, i detected a start bit!
• oh look here are more bits coming in which match my baud rate settings! (timeout hasn't occurred, and not too fast to be considered noise, etc)
• for each bit, starting index 0, if bit is high, put a 1 into the shift register, else put a zero into the shift register
• after the x number of data bits (could be 8-10 data bits in a serial frame) process is finished, and set flag for microcontroller to read my receive data register!

All of this is followed of course by 1 or 2 stop bits, and then the data line is kept at whatever idle level (usually high?) until the next transmission is detected.

Same style of thinking is used for bit-banging by software serial - as the pin level changes, increase the bit index and set/reset the bit on a "received byte" variable. It's essentially based on endian-ness of the system (little or big endian) and the fact that programmers like to use 0-indexing and starting at the lower end of a variable. Hardware UART transmit shift registers usually shift data out "backwards" than what you expect, as you mentioned in your question.