Timeline for How can I specify "don't care" signals in VHDL?
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
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| Sep 29, 2016 at 7:42 | history | edited | Fritz | CC BY-SA 3.0 |
Clarify optimization potential
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| Aug 11, 2016 at 19:33 | history | tweeted | twitter.com/StackElectronix/status/763820760049786880 | ||
| Jun 16, 2016 at 18:50 | history | edited | Fritz | CC BY-SA 3.0 |
Improve introduction
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| Aug 5, 2014 at 23:00 | answer | added | Carl | timeline score: 7 | |
| Apr 22, 2014 at 8:27 | vote | accept | Fritz | ||
| Apr 22, 2014 at 8:27 | vote | accept | Fritz | ||
| Apr 22, 2014 at 8:27 | |||||
| Apr 17, 2014 at 14:27 | answer | added | fru1tbat | timeline score: 12 | |
| Apr 17, 2014 at 8:15 | comment | added | Fritz | I hope the example makes it more clear what I want to achieve. | |
| Apr 17, 2014 at 8:15 | history | edited | Fritz | CC BY-SA 3.0 |
Added example for clarification.
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| Apr 16, 2014 at 20:11 | comment | added | fru1tbat |
Could you elaborate on what you're trying to do with write_address and write_data? What optimization do you expect to take place?
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| Apr 16, 2014 at 18:13 | history | asked | Fritz | CC BY-SA 3.0 |