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Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.

EDIT: (after reading the answer) Given that the rise/fall times are not that crucial and the fact that sample and hold periods matter the most, please, correct me if I am wrong on the following:

According to the timing diagram below, the best time to start sample would be on the falling edge of the TRIG or CLK clocks because after first half cycle (when any of the clocks go high) the VIDEO signal is still not reset?

enter image description hereenter image description here

Currently, I drive the ADC with TRIG clock and sampling starts on the rising edge of the TRIG. Therefore, after half cycle of the TRIG when it goes low and the ADC switches to 'hold' state, the VIDEO signal is reset. This might not be enough time to charge the SHA capacitor?

EDIT2: added a sampling clock for ADC. Which clock would be safer to drive the ADC with: SAMP or TRIG (SAMP is inverse of TRIG)?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.

EDIT: (after reading the answer) Given that the rise/fall times are not that crucial and the fact that sample and hold periods matter the most, please, correct me if I am wrong on the following:

According to the timing diagram below, the best time to start sample would be on the falling edge of the TRIG or CLK clocks because after first half cycle (when any of the clocks go high) the VIDEO signal is still not reset?

enter image description here

Currently, I drive the ADC with TRIG clock and sampling starts on the rising edge of the TRIG. Therefore, after half cycle of the TRIG when it goes low and the ADC switches to 'hold' state, the VIDEO signal is reset. This might not be enough time to charge the SHA capacitor?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.

EDIT: (after reading the answer) Given that the rise/fall times are not that crucial and the fact that sample and hold periods matter the most, please, correct me if I am wrong on the following:

According to the timing diagram below, the best time to start sample would be on the falling edge of the TRIG or CLK clocks because after first half cycle (when any of the clocks go high) the VIDEO signal is still not reset?

enter image description here

Currently, I drive the ADC with TRIG clock and sampling starts on the rising edge of the TRIG. Therefore, after half cycle of the TRIG when it goes low and the ADC switches to 'hold' state, the VIDEO signal is reset. This might not be enough time to charge the SHA capacitor?

EDIT2: added a sampling clock for ADC. Which clock would be safer to drive the ADC with: SAMP or TRIG (SAMP is inverse of TRIG)?

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Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.  

EDIT: (after reading the answer) Given that the rise/fall times are not that crucial and the fact that sample and hold periods matter the most, please, correct me if I am wrong on the following:

According to the timing diagram below, the best time to start sample would be on the falling edge of the TRIG or CLK clocks because after first half cycle (when any of the clocks go high) the VIDEO signal is still not reset?

enter image description here

Currently, I drive the ADC with TRIG clock and sampling starts on the rising edge of the TRIG. Therefore, after half cycle of the TRIG when it goes low and the ADC switches to 'hold' state, the VIDEO signal is reset. This might not be enough time to charge the SHA capacitor?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.  

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.

EDIT: (after reading the answer) Given that the rise/fall times are not that crucial and the fact that sample and hold periods matter the most, please, correct me if I am wrong on the following:

According to the timing diagram below, the best time to start sample would be on the falling edge of the TRIG or CLK clocks because after first half cycle (when any of the clocks go high) the VIDEO signal is still not reset?

enter image description here

Currently, I drive the ADC with TRIG clock and sampling starts on the rising edge of the TRIG. Therefore, after half cycle of the TRIG when it goes low and the ADC switches to 'hold' state, the VIDEO signal is reset. This might not be enough time to charge the SHA capacitor?

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Rise/fall time constrains for ADC?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.