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A PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

A Ternary NAND could be this:

^{simulate this circuit}

A Ternary NOR could be this:

^{simulate this circuit}

I would assume more complicated ternary gates could be made based on similar principles.

A PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

A Ternary NOR could be this:

^{simulate this circuit}

Truth Table:

00 0
0+ -
0- +
+- 0
++ -
-- +

A Ternary NAND could be this:

^{simulate this circuit}

Truth Table:

00 0
0+ 0
0- 0
+- 0
-- +
++ -

I would assume more complicated ternary gates could be made based on similar principles.

It's interesting to note that a major disadvantage of this topology is the loss of speed due to RC settling times where the C is inherent capacitance of the transistors. One possible advantage of this may be the required low-voltage and therefore low power draw of the circuits.

A PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

A Trit adder could be this:

^{simulate this circuit}

I would assume more complicated ternary gates could be made based on similar principles.

A PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

A Ternary NAND could be this:

^{simulate this circuit}

A Ternary NOR could be this:

^{simulate this circuit}

I would assume more complicated ternary gates could be made based on similar principles.

One method would be to use two comparators at two bias levels which would create your 3 values: 00=0, 01=1, 11=2. Then you would output 3 different levels depending on the comparator output. 0, 0.5, and 1 for instance. That would then get sent into the next set of ternary gates.

A simple differential pair could be used as the comparator.

After edit to question and need for balanced ternary gates, a different simpler topology became clear to me. An PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

I would assume more complicated ternary gates could be made based on similar principles.

A PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

A Trit adder could be this:

^{simulate this circuit}

I would assume more complicated ternary gates could be made based on similar principles.