I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes samples operates on 100 MHz clock. The problem is how can I interface these two modules?

My first thought was to use an asynchronous FIFO, but after search I figured out that it is impossible! Writing clock is much slower than reading side. I found a formula to calculate the depth of the FIFO (here) but it failed, giving me a negative answer! I didn't know what my "burst" is, so I assumed it to be 1 as the controller gives one sample every 16 clock cycles.

So, do you have any clue of solving this problem?

Thanks in advance.

I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes samples operates on 100 MHz clock. The problem is how can I interface these two modules?

My first thought was to use an asynchronous FIFO, but after search I figured out that it is impossible! Writing clock is much slower than reading side. I found a formula to calculate the depth of the FIFO (here) but it failed, giving me a negative answer! I didn't know what my "burst" is, so I assumed it to be 1 as the controller gives one sample every 16 clock cycles.

So, do you have any clue of solving this problem?