Timeline for Ring counter in verilog
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Feb 17, 2015 at 8:06 | comment | added | gstorto | @Plutoniumsmuggler Yes, I understand. You should never define the signal connected to an output from your DUT as regs, nor assign values to them, because it may lead to two entities driving the same signal. A good simulator would detect this condition, give an error and stop the simulation. | |
| Feb 17, 2015 at 6:34 | vote | accept | Plutonium smuggler | ||
| Feb 17, 2015 at 6:34 | comment | added | Plutonium smuggler | Actually, I did all of this. But my design wouldnt work because as mentioned in the comments above, I was initialising an output port in test bench. So inorder to find out the error, I temporarily removed all non critical functionality like load and reset with an assumption that my counter should be able to shift any initial value as well. Thats why you see an initial block in main module. As far as non blocking assignment is concerned, i'll definitely change it now that you have pointed. | |
| Feb 17, 2015 at 6:24 | history | edited | gstorto | CC BY-SA 3.0 |
added 363 characters in body
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| Feb 17, 2015 at 6:19 | history | edited | gstorto | CC BY-SA 3.0 |
added 363 characters in body
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| Feb 17, 2015 at 6:08 | history | answered | gstorto | CC BY-SA 3.0 |