We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns (1 oz) in our designs, so 'high thickness' for us means, 70 (2 oz) or 105 (3 oz).

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns (1 oz) in our designs, so 'high thickness' for us means, 70 (2 oz) or 105 (3 oz).

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1. It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2. Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3. If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4. About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5. When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns in our designs, so 'high thickness' for us means, 70 or 105.

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns (1 oz) in our designs, so 'high thickness' for us means, 70 (2 oz) or 105 (3 oz).

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper density. So far we've only used 35 microns in our designs, so 'high density' for us means, 70 or 105.

We do not know what are the things to watch out for with denser copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher densities possible?

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns in our designs, so 'high thickness' for us means, 70 or 105.

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?