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EDIT, COMMENTS:

TL;DR: Data doesn't conclusively suggest you can do this, but it seems to be worth trying.

The data from IPC-2152 (more in the answers below) is intriguing, but doesn't seem to conclusively say that what I'm proposing is possible. However, it does say that inner layer traces aren't thermally handicapped: in fact, it seems inner layer traces have lower thermal resistance than their outer layer counterparts (at least in still air).

Let's do a quick calculation to see how this would play out, using the following parameters

  • a common 1oz/0.5oz/0.5oz/1oz 4-layer stack-up
  • 4 equally sized traces of a width that results in a 1 ohm trace resistance (large, yes, I know) for the outer layers and 2 ohms (since the copper thickness is half) on the inner layers.
  • A 10V potential across the traces

schematic

simulate this circuit – Schematic created using CircuitLab

In this case, we would see 10A on the outer layers and 5A on the inner layers. Power dissipation is then I^2R, which is 100W (10A^2 * 1 Ohm) in the outer traces and 50W (5A^2 * 2 Ohms) on the inner traces.

Given that we know the thermal conductivity of the inner traces is likely to be no worse than the outer layers, it looks like it's at least worth trying a 4-layer design, since the key worry (that the inner traces will run much hotter than the outer traces) doesn't seem to be a concern.

=================================== END EDIT

Original question:

I'm doing some high-current (40A continuous in worst case) traces on a 4-layer PCB, and I'm trying to get the space consumption down.

I've had success in the past with mirroring traces -- half of the trace goes on the top layer, and half goes on the bottom. For example, a 1" wide trace would become a 0.5" trace on the bottom and a 0.5" trace on the top.

But what about inner layers? On a 4-layer board, can I do the same across all 4 layers (e.g. 4x 0.25" traces, assuming all 4 layers are the same copper weight)?

My intuition says no -- the inner traces are much worse at shedding heat, so this may become a problem. But then again, copper has a positive temperature coefficient of resistivity, so perhaps these things balance to an equilibrium?

My question, in parts, is this:

  • Can I distribute power traces across outer and inner layers?

  • Has anyone done this and had luck/success?

  • Do the inner layer traces have to be thicker/thinner than the outer layer traces?

I'm doing some high-current (40A continuous in worst case) traces on a 4-layer PCB, and I'm trying to get the space consumption down.

I've had success in the past with mirroring traces -- half of the trace goes on the top layer, and half goes on the bottom. For example, a 1" wide trace would become a 0.5" trace on the bottom and a 0.5" trace on the top.

But what about inner layers? On a 4-layer board, can I do the same across all 4 layers (e.g. 4x 0.25" traces, assuming all 4 layers are the same copper weight)?

My intuition says no -- the inner traces are much worse at shedding heat, so this may become a problem. But then again, copper has a positive temperature coefficient of resistivity, so perhaps these things balance to an equilibrium?

My question, in parts, is this:

  • Can I distribute power traces across outer and inner layers?

  • Has anyone done this and had luck/success?

  • Do the inner layer traces have to be thicker/thinner than the outer layer traces?

EDIT, COMMENTS:

TL;DR: Data doesn't conclusively suggest you can do this, but it seems to be worth trying.

The data from IPC-2152 (more in the answers below) is intriguing, but doesn't seem to conclusively say that what I'm proposing is possible. However, it does say that inner layer traces aren't thermally handicapped: in fact, it seems inner layer traces have lower thermal resistance than their outer layer counterparts (at least in still air).

Let's do a quick calculation to see how this would play out, using the following parameters

  • a common 1oz/0.5oz/0.5oz/1oz 4-layer stack-up
  • 4 equally sized traces of a width that results in a 1 ohm trace resistance (large, yes, I know) for the outer layers and 2 ohms (since the copper thickness is half) on the inner layers.
  • A 10V potential across the traces

schematic

simulate this circuit – Schematic created using CircuitLab

In this case, we would see 10A on the outer layers and 5A on the inner layers. Power dissipation is then I^2R, which is 100W (10A^2 * 1 Ohm) in the outer traces and 50W (5A^2 * 2 Ohms) on the inner traces.

Given that we know the thermal conductivity of the inner traces is likely to be no worse than the outer layers, it looks like it's at least worth trying a 4-layer design, since the key worry (that the inner traces will run much hotter than the outer traces) doesn't seem to be a concern.

=================================== END EDIT

Original question:

I'm doing some high-current (40A continuous in worst case) traces on a 4-layer PCB, and I'm trying to get the space consumption down.

I've had success in the past with mirroring traces -- half of the trace goes on the top layer, and half goes on the bottom. For example, a 1" wide trace would become a 0.5" trace on the bottom and a 0.5" trace on the top.

But what about inner layers? On a 4-layer board, can I do the same across all 4 layers (e.g. 4x 0.25" traces, assuming all 4 layers are the same copper weight)?

My intuition says no -- the inner traces are much worse at shedding heat, so this may become a problem. But then again, copper has a positive temperature coefficient of resistivity, so perhaps these things balance to an equilibrium?

My question, in parts, is this:

  • Can I distribute power traces across outer and inner layers?

  • Has anyone done this and had luck/success?

  • Do the inner layer traces have to be thicker/thinner than the outer layer traces?

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Can a high current trace be on outer and inner layers at the same time?

I'm doing some high-current (40A continuous in worst case) traces on a 4-layer PCB, and I'm trying to get the space consumption down.

I've had success in the past with mirroring traces -- half of the trace goes on the top layer, and half goes on the bottom. For example, a 1" wide trace would become a 0.5" trace on the bottom and a 0.5" trace on the top.

But what about inner layers? On a 4-layer board, can I do the same across all 4 layers (e.g. 4x 0.25" traces, assuming all 4 layers are the same copper weight)?

My intuition says no -- the inner traces are much worse at shedding heat, so this may become a problem. But then again, copper has a positive temperature coefficient of resistivity, so perhaps these things balance to an equilibrium?

My question, in parts, is this:

  • Can I distribute power traces across outer and inner layers?

  • Has anyone done this and had luck/success?

  • Do the inner layer traces have to be thicker/thinner than the outer layer traces?