2 minor correction
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Trace of 1mm length 0.2mm width, 0.35mm above power plane will have comparable inductance of 0.4nH - which again makes capacitors less efficient, thus trying to limit capacitors trace length to a fraction of a mm and making them as wide as possible makes a lot of sense.

Trace length 0.2mm width, 0.35mm above power plane will have comparable inductance of 0.4nH - which again makes capacitors less efficient, thus trying to limit capacitors trace length to a fraction of a mm and making them as wide as possible makes a lot of sense.

Trace of 1mm length 0.2mm width, 0.35mm above power plane will have comparable inductance of 0.4nH - which again makes capacitors less efficient, thus trying to limit capacitors trace length to a fraction of a mm and making them as wide as possible makes a lot of sense.

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Capacitors made of X7R (and even more so Y5V) have huge capacity/voltage dependence. You can check this yourself at the excellent Murata products online characteristics browser (Simsurfing) at ttp://ds.murata.co.jp/software/simsurfing/en-us/

The ceramic capacitor voltage dependence is striking. It is normal for X7R capacitor to have no more then 30% of rated capacity at rated voltage. For example - 10uF Murata capacitor GRM21BR61C106KE15 (0805 package, X5R) rated for 16V will give you only 2.3uF capacity with 12V DC applied at 25C temperature. Y5V is much worse in this respect.

In order to obtain close to 10uF capacity you have to use 25V rated GRM32DR71E106K (1210 case, X7R) which gives 7.5uF under same conditions.

Other then DC voltage (and temperature) dependencies, Real "ceramic chip capacitor" have strong frequency dependence when acting as power decoupling shunts. Murata's site provides |Z|, R and X frequency dependencies graphs for their capacitors, browsing these gives you an insight into actual performance of the part we call "capacitor" at different frequencies.

Real ceramic capacitor can be modeled by an ideal capacitor (C) connected in series with internal resistance (Resr) and inductance (Lesl). There is also R-isolation in parallel with C, but unless you go over capacitor's rated voltage it is unimportant for power decoupling applications.

schematic

simulate this circuit – Schematic created using CircuitLab

Thus chip ceramic capacitors will act as capacitors only up to a certain frequency (self resonant for the serial LC contour which real capacitor is in fact), above which they start to act as inductors. This frequency Fres is equal to sqrt(1/LC) and is determined by both the ceramics composition and capacitor geometry - generally smaller packages have higher Fres Also, capacitors have a purely resistive component (Resr) which results mostly from the losses in the ceramic and determines the minimum impedance the capacitor can provide. It is usually in the mili-Ohms range.

In practice for good decoupling I use 3 types of capacitors.

Higher capacity about 10uF in 1210 or 1208 package per integrated circuit, that covers 10KHz to 10MHz with less then 10-15 mili-Ohm shunt for power line noise.

Then per every IC power pin I put two capacitors - one 100nF in 0806 package covering 1MHz to 40MHz with 20 mili-Ohm shunt, and one 1nF in 0603 package, covering 80MHz to 400MHz with 30 mili-ohm shunt. This more or less covers 10KHz to 400MHz range for filtering out power line noise.

For sensitive power circuits (like PLL digital and especially analog power) I put ferrite beads (again, Murata has characteristics browser for those) rated 100 to 300 Ohms at 100Mhz. It's also a good idea to separate grounds between sensitive and regular power circuits. Thus overall outline of IC power plan looks like this, with 10uF C6 per IC package, and 1nF/100nF C4/C5 per each power pin:

schematic

simulate this circuit

Speaking about routing and placement - power and ground is routed to capacitors first, only at capacitors we connect to power and ground planes through vias. 1nF capacitors are placed closer to IC pins. Capacitors have to be placed as close to power pins as possible, no further then 1mm trace length from capacitor pad to IC pad.

Vias and even short traces on PCB pose a significant inductance for the frequencies and capacitance we're dealing with. For example, 0.5mm diameter via in 1.5mm thick PCB has 1.1nH inductance from top to bottom layer. For 1nF capacitor that results in Fres equal to only 15MHz. Thus, connecting a capacitor through via makes 1nF capacitor low Resr unusable at frequencies above 15MHz. In fact 1.1nH reactance at 100MHz is as much as 0.7 Ohm.

Trace length 0.2mm width, 0.35mm above power plane will have comparable inductance of 0.4nH - which again makes capacitors less efficient, thus trying to limit capacitors trace length to a fraction of a mm and making them as wide as possible makes a lot of sense.