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typo

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edited Nov 1, 2015 at 13:56

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As you know, you use the upper part of the structure (from Vout to Vcc) to set the 1's and the lower part of the structure (from Vout to Vss) to set the 0's.

You can do this directly from the function expression. For example, let say your function is F=A·B+C. I've chosen a different (and shorter function) for a simpler illustration of the method.*

The upper part is easy (A and B* in series for AND) and C in parallel (for the OR part). The variables enter negated into the PMOS gate, because the PMOS will turn ON for 0 V (and not 5 V).

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Then the lower part must implement the 0's. Recalling the De Morgan Theorem, by negating F, AND becomes OR and viceversa. Applying to our function: we'll get F*=(A*+B)·C*

Therefore, in the lower part we have AA* and B*B that are in parallel while C is in series. The variables doesn't enter negated into the NMOS gates because NMOS turn ON for 5V.

This method can be applied also to your original function, it just needs much more space!

As you know, you use the upper part of the structure (from Vout to Vcc) to set the 1's and the lower part of the structure (from Vout to Vss) to set the 0's.

You can do this directly from the function expression. For example, let say your function is F=A·B+C. I've chosen a different (and shorter function) for a simpler illustration of the method.*

The upper part is easy (A and B* in series for AND) and C in parallel (for the OR part). The variables enter negated into the PMOS gate, because the PMOS will turn ON for 0 V (and not 5 V).

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Then the lower part must implement the 0's. Recalling the De Morgan Theorem, by negating F, AND becomes OR and viceversa. Applying to our function: we'll get F*=(A*+B)·C*

Therefore, in the lower part we have A and B* that are in parallel while C is in series. The variables doesn't enter negated into the NMOS gates because NMOS turn ON for 5V.

This method can be applied also to your original function, it just needs much more space!

As you know, you use the upper part of the structure (from Vout to Vcc) to set the 1's and the lower part of the structure (from Vout to Vss) to set the 0's.

You can do this directly from the function expression. For example, let say your function is F=A·B+C. I've chosen a different (and shorter function) for a simpler illustration of the method.*

The upper part is easy (A and B* in series for AND) and C in parallel (for the OR part). The variables enter negated into the PMOS gate, because the PMOS will turn ON for 0 V (and not 5 V).

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Then the lower part must implement the 0's. Recalling the De Morgan Theorem, by negating F, AND becomes OR and viceversa. Applying to our function: we'll get F*=(A*+B)·C*

Therefore, in the lower part we have A* and B that are in parallel while C is in series. The variables doesn't enter negated into the NMOS gates because NMOS turn ON for 5V.

This method can be applied also to your original function, it just needs much more space!

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created Nov 1, 2015 at 13:41

Roger C.

2.2k
1
12
12

As you know, you use the upper part of the structure (from Vout to Vcc) to set the 1's and the lower part of the structure (from Vout to Vss) to set the 0's.

You can do this directly from the function expression. For example, let say your function is F=A·B+C. I've chosen a different (and shorter function) for a simpler illustration of the method.*

The upper part is easy (A and B* in series for AND) and C in parallel (for the OR part). The variables enter negated into the PMOS gate, because the PMOS will turn ON for 0 V (and not 5 V).

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Then the lower part must implement the 0's. Recalling the De Morgan Theorem, by negating F, AND becomes OR and viceversa. Applying to our function: we'll get F*=(A*+B)·C*

Therefore, in the lower part we have A and B* that are in parallel while C is in series. The variables doesn't enter negated into the NMOS gates because NMOS turn ON for 5V.

This method can be applied also to your original function, it just needs much more space!