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4 Copy edited, incl. [its = possessive, it's = "it is" or "it has".].
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Decoupling Capscapacitors on Bottom Layerthe bottom layer?

I'm using 0.01uF01 uF decoupling capscapacitors in 0805 packagea 0805 package, on each VccVcc/GND pair of my CPLDsCPLDs. So, around 8 capseight capacitors in total). I find it a bit easier to route the board if the decoupling capscapacitors are placed on the bottom layer and connected to the VccVcc and GND pins of the CPLD/MCU using viasvias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the capcapacitor.

My bottom layer also serves as a ground plane. (itsit's a two-layer board, so I don't have a VccVcc plane), and so I don't need to connect the ground pin of the capcapacitor using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

The thick trace coming toward the capcapacitor is VccVcc (3.3V3 V) and itsit's connected to another thick trace that comes straight from the power source. I provide VccVcc to all the capscapacitors in this way. Is it a good practice to connect all the decoupling capscapacitors in such a way or will I run into problems down the road?

An alternatealternative way that I've seen being used is that there is a single trace for VccVcc and another for GND that runs from the power source. The decoupling capscapacitors then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick VccVcc and GND traces running from a single point. A bit like my VccVcc approach described in the previous paragraph, but also adopted for GND.

Here are some more pictures of the decoupling capscapacitors. I think out of these the best is the one where the capcapacitor is at the top layer - do you guys agree? 

I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF001 uF to 0.1uF1 uF was specified in Altera's documentation and so I settled at 0.01uF01 uF. Unfortunately, even though I mentally noted that I'll need another capcapacitor at less 3cm3 cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap1 uF capacitor in parallel to each Vdd/GndGND pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz5 kHz). The uCmicrocontroller will be at 8MHz8 MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each capcapacitor to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

Here's the CPLD with 1uF caps1 uF capacitors and a star-network for VccVcc. Does this look like a better design?

My worry now is that the star point (or area) will interfere with the ground plane, as they're on the same layer. Also note, I'm connecting VccVcc to just the larger caps' Vcccapacitors' Vcc pin. Is this good or should I connect VccVcc to each capacitor individually?

Oh and please don't mind the illogical cap.capacitor labeling. I'm going to fix it now.

Decoupling Caps on Bottom Layer?

I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Here are some more pictures of the decoupling caps. I think out of these the best is the one where the cap is at the top layer - do you guys agree? I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF to 0.1uF was specified in Altera's documentation and so I settled at 0.01uF. Unfortunately, even though I mentally noted that I'll need another cap at less 3cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap in parallel to each Vdd/Gnd pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz). The uC will be at 8MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each cap to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

Here's the CPLD with 1uF caps and a star-network for Vcc. Does this look like a better design?

My worry now is that the star point (or area) will interfere with the ground plane, as they're on the same layer. Also note, I'm connecting Vcc to just the larger caps' Vcc pin. Is this good or should I connect Vcc to each capacitor individually?

Oh and please don't mind the illogical cap. labeling. I'm going to fix it now.

Decoupling capacitors on the bottom layer?

I'm using 0.01 uF decoupling capacitors in a 0805 package, on each Vcc/GND pair of my CPLDs. So, around eight capacitors in total). I find it a bit easier to route the board if the decoupling capacitors are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the capacitor.

My bottom layer also serves as a ground plane. (it's a two-layer board, so I don't have a Vcc plane), and so I don't need to connect the ground pin of the capacitor using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

The thick trace coming toward the capacitor is Vcc (3.3 V) and it's connected to another thick trace that comes straight from the power source. I provide Vcc to all the capacitors in this way. Is it a good practice to connect all the decoupling capacitors in such a way or will I run into problems down the road?

An alternative way that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling capacitors then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Here are some more pictures of the decoupling capacitors. I think out of these the best is the one where the capacitor is at the top layer - do you guys agree? 

I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001 uF to 0.1 uF was specified in Altera's documentation and so I settled at 0.01 uF. Unfortunately, even though I mentally noted that I'll need another capacitor at less 3 cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1 uF capacitor in parallel to each Vdd/GND pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5 kHz). The microcontroller will be at 8 MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each capacitor to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

Here's the CPLD with 1 uF capacitors and a star-network for Vcc. Does this look like a better design?

My worry now is that the star point (or area) will interfere with the ground plane, as they're on the same layer. Also note, I'm connecting Vcc to just the larger capacitors' Vcc pin. Is this good or should I connect Vcc to each capacitor individually?

Oh and please don't mind the illogical capacitor labeling. I'm going to fix it now.

3 added 527 characters in body
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I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?


enter image description here

Figure 2

enter image description here

Figure 3

Here are some more pictures of the decoupling caps. I think out of these the best is the one where the cap is at the top layer - do you guys agree? I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF to 0.1uF was specified in Altera's documentation and so I settled at 0.01uF. Unfortunately, even though I mentally noted that I'll need another cap at less 3cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap in parallel to each Vdd/Gnd pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz). The uC will be at 8MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each cap to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

If this is the case, should I have a ground plane at all? The only other chips on the board are an MCU and another CLPD (same device, though). Other than that, it's just a bunch of headers, connectors and passive elements.


Here's the CPLD with 1uF caps and a star-network for Vcc. Does this look like a better design?

enter image description here

My worry now is that the star point (or area) will interfere with the ground plane, as they're on the same layer. Also note, I'm connecting Vcc to just the larger caps' Vcc pin. Is this good or should I connect Vcc to each capacitor individually?

Oh and please don't mind the illogical cap. labeling. I'm going to fix it now.

I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?


enter image description here

Figure 2

enter image description here

Figure 3

Here are some more pictures of the decoupling caps. I think out of these the best is the one where the cap is at the top layer - do you guys agree? I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF to 0.1uF was specified in Altera's documentation and so I settled at 0.01uF. Unfortunately, even though I mentally noted that I'll need another cap at less 3cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap in parallel to each Vdd/Gnd pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz). The uC will be at 8MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each cap to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

If this is the case, should I have a ground plane at all? The only other chips on the board are an MCU and another CLPD (same device, though). Other than that, it's just a bunch of headers, connectors and passive elements.

I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?


enter image description here

Figure 2

enter image description here

Figure 3

Here are some more pictures of the decoupling caps. I think out of these the best is the one where the cap is at the top layer - do you guys agree? I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF to 0.1uF was specified in Altera's documentation and so I settled at 0.01uF. Unfortunately, even though I mentally noted that I'll need another cap at less 3cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap in parallel to each Vdd/Gnd pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz). The uC will be at 8MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each cap to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

If this is the case, should I have a ground plane at all? The only other chips on the board are an MCU and another CLPD (same device, though). Other than that, it's just a bunch of headers, connectors and passive elements.


Here's the CPLD with 1uF caps and a star-network for Vcc. Does this look like a better design?

enter image description here

My worry now is that the star point (or area) will interfere with the ground plane, as they're on the same layer. Also note, I'm connecting Vcc to just the larger caps' Vcc pin. Is this good or should I connect Vcc to each capacitor individually?

Oh and please don't mind the illogical cap. labeling. I'm going to fix it now.

2 added 1762 characters in body
source | link

I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?


enter image description here

Figure 2

enter image description here

Figure 3

Here are some more pictures of the decoupling caps. I think out of these the best is the one where the cap is at the top layer - do you guys agree? I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF to 0.1uF was specified in Altera's documentation and so I settled at 0.01uF. Unfortunately, even though I mentally noted that I'll need another cap at less 3cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap in parallel to each Vdd/Gnd pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz). The uC will be at 8MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each cap to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

If this is the case, should I have a ground plane at all? The only other chips on the board are an MCU and another CLPD (same device, though). Other than that, it's just a bunch of headers, connectors and passive elements.

I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?

I'm using 0.01uF decoupling caps in 0805 package, on each Vcc/GND pair of my CPLDs. So, around 8 caps in total). I find it a bit easier to route the board if the decoupling caps are placed on the bottom layer and connected to the Vcc and GND pins of the CPLD/MCU using vias.

Is this a good practice? I understand the aim is to minimize the current loop between the chip and the cap.

My bottom layer also serves as a ground plane. (its a two-layer board, so I don't have a Vcc plane) and so I don't need to connect the ground pin of the cap using vias. Obviously, the chip's GND pin is connected using a via. Here's a picture that illustrates this better:

enter image description here

The thick trace coming toward the cap is Vcc (3.3V) and its connected to another thick trace that comes straight from the power source. I provide Vcc to all the caps in this way. Is it a good practice to connect all the decoupling caps in such a way or will I run into problems down the road?

An alternate that I've seen being used is that there is a single trace for Vcc and another for GND that runs from the power source. The decoupling caps then 'tap' into those traces. I noticed that in that approach there was no ground plane - just thick Vcc and GND traces running from a single point. A bit like my Vcc approach described in the previous paragraph, but also adopted for GND.

Which approach would be better?


enter image description here

Figure 2

enter image description here

Figure 3

Here are some more pictures of the decoupling caps. I think out of these the best is the one where the cap is at the top layer - do you guys agree? I'll obviously need one via for the GND pin if I want it to connect to the ground plane. Regarding the value, 0.001uF to 0.1uF was specified in Altera's documentation and so I settled at 0.01uF. Unfortunately, even though I mentally noted that I'll need another cap at less 3cm, I didn't remember to implement it on the schematic. Based on the suggestions here, I'll also add 1uF cap in parallel to each Vdd/Gnd pair.

Regarding power - I'll be using 100 logic elements for a 100-bit shift register. The frequency of operation is largely dependent on the SPI interface of the MCU that I'll use to read the shift register. I'll be using the slowest frequency that the AVR Mega 128L allows for SPI (i.e. 62.5kHz). The uC will be at 8MHz using its internal oscillator.

Reading the answers below, I'm now quite concerned about my ground plane. If I understand Olin's answer, I should not connect the GND pin of each cap to the ground plane. Instead, I should connect the GND pins to the main GND net on the top layer and then connect that GND network to the main return. Am I correct here?

If this is the case, should I have a ground plane at all? The only other chips on the board are an MCU and another CLPD (same device, though). Other than that, it's just a bunch of headers, connectors and passive elements.

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