Timeline for FIFO in VHDL : ERROR:HDLParsers:3324
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
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| Nov 23, 2015 at 10:07 | vote | accept | Cabs | ||
| S Nov 20, 2015 at 20:01 | history | suggested | user8352 |
It's a Xilinx XST error message
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| Nov 20, 2015 at 19:06 | review | Suggested edits | |||
| S Nov 20, 2015 at 20:01 | |||||
| Nov 20, 2015 at 19:05 | answer | added | user8352 | timeline score: 2 | |
| Nov 20, 2015 at 15:48 | comment | added | Botnic | The error tells you exactly where the problem is: In U102:Led_out you have one parameter missing (Dout). | |
| Nov 20, 2015 at 14:22 | comment | added | MrSmith42 | For easier reading you should try to use a coding convention instead of writing things sometimes uppercase and sometimes lower case. (also indention rules ...) | |
| Nov 20, 2015 at 13:45 | comment | added | user16324 | Duplicate of stackoverflow.com/questions/33709155/… Also note, you'd likely have spotted this mistake immediately if you'd used named association. How much time have you wasted by avoiding the extra typing? | |
| Nov 20, 2015 at 13:28 | history | asked | Cabs | CC BY-SA 3.0 |