Timeline for Verilog: slow clock generator module (1 Hz from 50 MHz)
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Sep 15, 2022 at 22:31 | history | edited | ocrdu | CC BY-SA 4.0 |
deleted 4 characters in body; edited title
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| Sep 15, 2022 at 19:53 | history | edited | toolic | CC BY-SA 4.0 |
added 4 characters in body; edited title
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| Sep 25, 2017 at 18:40 | answer | added | Bhumanyoo Varshney | timeline score: 1 | |
| Dec 6, 2015 at 2:03 | vote | accept | funky-nd | ||
| Dec 6, 2015 at 1:25 | comment | added | The Photon | You got your answer, but in the future please add a comment telling us which line is the one with the error (line 74, in this case). | |
| Dec 6, 2015 at 0:27 | answer | added | toolic | timeline score: 1 | |
| Dec 6, 2015 at 0:25 | review | First posts | |||
| Dec 6, 2015 at 0:28 | |||||
| Dec 6, 2015 at 0:21 | history | asked | funky-nd | CC BY-SA 3.0 |