With many ADCs, the maximum source impedance is ultimately dominated by pin leakage current, in particular those embedded in microcontrollers when multiplexed with digital I/O functions. This is due to a number of causes, but always exists.

Charge redistribution devices are a bit more complex.

This has nothing to do with the time taken to charge the sample capacitor (which determines the maximum source resistance vs. sample rate)

On page 1380 of the data sheet we find that Vdd powered pins have a worst case low input leakage of 30nA when the pin is at 0V; as this Is the higher of the leakage currents, I will use this value to figure out the maximum source impedance.

To prevent greater than 1% error, we must drive the pin with at least 100 times the leakage (3 microamps), so at midrange (1.65V if you are converting across 3.3V) we get 550kohm, which lines up well with the maximum sample rate vs. source impedance from the previous answer.

If I wanted 0.1% error or less, I would keep the source impedance below 50k. Note that it is common to drive an ADC with a very low impedance source with a device designed for the task to ensure input leakage is not an issue.

This is an estimate, of course, but it seems reasonably accurate.

With many ADCs, the maximum source impedance is ultimately dominated by pin leakage current, in particular those embedded in microcontrollers when multiplexed with digital I/O functions. This is due to a number of causes, but always exists.

Charge redistribution devices are a bit more complex.

This has nothing to do with the time taken to charge the sample capacitor (which determines the maximum source resistance vs. sample rate)

On page 1380 of the data sheet we find that Vdd powered pins have a worst case low input leakage of 30nA when the pin is at 0V; as this Is the higher of the leakage currents, I will use this value to figure out the maximum source impedance.

To prevent greater than 1% error, we must drive the pin with at least 100 times the leakage (3 microamps), so at midrange (1.65V if you are converting across 3.3V) we get 550kohm, which lines up well with the maximum sample rate vs. source impedance from the previous answer.

If I wanted 0.1% error or less, I would keep the source impedance below 50k. Note that it is common to drive an ADC with a very low impedance source with a device designed for the task to ensure input leakage is not an issue.

This is an estimate, of course, but it seems reasonably accurate.

With any ADC, the maximum source impedance is ultimately dominated by pin leakage current. This is due to a number of causes, but always exists.

This has nothing to do with the time taken to charge the sample capacitor (which determines the maximum source resistance vs. sample rate)

On page 1380 of the data sheet we find that Vdd powered pins have a worst case low input leakage of 30nA when the pin is at 0V; as this Is the higher of the leakage currents, I will use this value to figure out the maximum source impedance.

To prevent greater than 1% error, we must drive the pin with at least 100 times the leakage (3 microamps), so at midrange (1.65V if you are converting across 3.3V) we get 550kohm, which lines up well with the maximum sample rate vs. source impedance from the previous answer.

If I wanted 0.1% error or less, I would keep the source impedance below 50k. Note that it is common to drive an ADC with a very low impedance source with a device designed for the task to ensure input leakage is not an issue.

This is an estimate, of course, but it seems reasonably accurate.

With many ADCs, the maximum source impedance is ultimately dominated by pin leakage current, in particular those embedded in microcontrollers when multiplexed with digital I/O functions. This is due to a number of causes, but always exists.

Charge redistribution devices are a bit more complex.

This has nothing to do with the time taken to charge the sample capacitor (which determines the maximum source resistance vs. sample rate)

On page 1380 of the data sheet we find that Vdd powered pins have a worst case low input leakage of 30nA when the pin is at 0V; as this Is the higher of the leakage currents, I will use this value to figure out the maximum source impedance.

To prevent greater than 1% error, we must drive the pin with at least 100 times the leakage (3 microamps), so at midrange (1.65V if you are converting across 3.3V) we get 550kohm, which lines up well with the maximum sample rate vs. source impedance from the previous answer.

If I wanted 0.1% error or less, I would keep the source impedance below 50k. Note that it is common to drive an ADC with a very low impedance source with a device designed for the task to ensure input leakage is not an issue.

This is an estimate, of course, but it seems reasonably accurate.