Timeline for How to generate sound in VHDL
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
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| Mar 7, 2016 at 8:20 | comment | added | Paebbels | So your design sends a signal of over 1 MHz.... That's far to fast. | |
| Mar 7, 2016 at 8:18 | comment | added | glassesRCool | @Paebbels the frequency is 50MHz | |
| Mar 7, 2016 at 0:41 | history | edited | uint128_t | CC BY-SA 3.0 |
Fixed grammar/indents/phrasing/links
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| Mar 7, 2016 at 0:36 | answer | added | uint128_t | timeline score: 4 | |
| Mar 7, 2016 at 0:06 | comment | added | Paebbels |
What's the frequency of clk? What pins did you assign? I don't think your audio chip accepts raw binary values.
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| Mar 6, 2016 at 23:56 | review | First posts | |||
| Mar 7, 2016 at 0:24 | |||||
| Mar 6, 2016 at 23:48 | history | asked | glassesRCool | CC BY-SA 3.0 |