Timeline for Blocking vs Non Blocking Assignments
Current License: CC BY-SA 3.0
3 events
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| Mar 15, 2016 at 16:21 | comment | added | The Photon | @ironstein, then you need to get rid of all those delay elements (#31, etc), as they are not synthesizable. To write for synthesis, provide a clock, build a state machine, and drive the output signals according to the FSM state. | |
| Mar 15, 2016 at 16:16 | comment | added | ironstein | #3 my testbench containg rx_done_tick as a signal right now, but it is will later be an output signal from the uart module. So, it is going to be synthesized. | |
| Mar 15, 2016 at 16:13 | history | answered | The Photon | CC BY-SA 3.0 |