Timeline for Modular PCB Design
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 16, 2011 at 16:42 | comment | added | Majenko | You are quite correct in your thinking. It turns the whole thing into one big shift register. | |
| Nov 16, 2011 at 15:47 | comment | added | Saad | I'm sort of confused... you see, I want to address the entire cascaded line of CPLDs as a single shift register. So, is CS is active, that means all chips' SPI is active. And if so, as the CLK works, the CPLDs down the line will 'automatically' get the data from the previous ones. I don't feel the need to address each CPLD individually. So if I shift the contents 120 times, some of the bits will spill over automatically. Is my thinking on this correct or am I missing something? Thanks for the response. | |
| Nov 16, 2011 at 13:04 | comment | added | Saad | Yes. Didn't realize that... now I feel embarrassed. CS/SS will be the same as for all chips, right? | |
| Nov 16, 2011 at 10:48 | history | answered | Majenko | CC BY-SA 3.0 |