Timeline for FPGA Frequency Divider
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
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| Mar 26, 2016 at 16:18 | vote | accept | Min_ah | ||
| Mar 26, 2016 at 15:47 | comment | added | andrsmllr |
What do you think is wrong with the waveform? Since you are toggeling adjclock at a rate of 200 Hz the clock frequency of adjclock will in fact only be 100 Hz.
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| Mar 26, 2016 at 15:32 | answer | added | uint128_t | timeline score: 0 | |
| Mar 26, 2016 at 15:20 | comment | added | Min_ah | There is no error at compile time, but for the ISIM simulator, I think there is something wrong with the waveform. | |
| Mar 26, 2016 at 15:07 | comment | added | uint128_t | You should add why it isn't working? Is the output the wrong frequency? Are there errors at compile time? Etc. | |
| Mar 26, 2016 at 15:00 | review | First posts | |||
| Mar 26, 2016 at 17:30 | |||||
| Mar 26, 2016 at 14:59 | history | asked | Min_ah | CC BY-SA 3.0 |