Timeline for How do you design a CMOS buffer with exact same delay of a CMOS inverter?
Current License: CC BY-SA 3.0
5 events
when toggle format | what | by | license | comment | |
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Jul 16, 2016 at 3:36 | comment | added | Dr. Ehsan Ali | I simulated the above circuit, there is still about 85ps mismatch. Measured at 50% signal level. | |
Jul 9, 2016 at 17:08 | vote | accept | Dr. Ehsan Ali | ||
Jul 6, 2016 at 9:56 | comment | added | Mario | Of course there are different ways to achieve the same result. Scaling an inverter could work as well. | |
Jul 6, 2016 at 9:38 | comment | added | Austin | If fiddling with the device characteristics is necessary to get the delays matched exactly, is it possible to just build a really slow inverter to match the upper pair? | |
Jul 6, 2016 at 8:01 | history | answered | Mario | CC BY-SA 3.0 |