Timeline for Help on defining the 8-layer stack-up for a high speed design
Current License: CC BY-SA 3.0
14 events
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| Aug 9, 2016 at 22:23 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Jul 11, 2016 at 9:00 | comment | added | Claudio Avi Chami | @nickagian I have done a lot of High Speed boards, always with two adjacent signals sandwiched between GND or between GND and VCC. Usually I would include the GND-GND sandwich on the top, close to the high speed devices. I always define one layer as 'x' and one as 'y' and where needed, make simulations to catch crosstalk issues that can still arise because it is impossible to maker perfect 'x' traces or 'y' traces, there are diagonals, etc. where crosstalk can appear. | |
| Jul 11, 2016 at 8:20 | comment | added | nickagian | @Neil_UK You are actually correct. I didn't say much about the application. But it seems I need almost all of these that you mention. I have high component density and need to have controlled impedance lines. Buried vias are not yet into consideration. Multiple grounds for heat dissipation would be a good idea. And of course EMC is a big issue, we need the CE mark. That's one reason why I would prefer top grounds for earthing shielding. | |
| Jul 11, 2016 at 8:17 | comment | added | nickagian | @ClaudioAviChami No 10 layers are not an option. But why do you recommend such a stack-up for 10-layers? I see you have again two adjacent signal layers. | |
| Jul 11, 2016 at 8:17 | comment | added | nickagian | @Marcus Müller I indeed have components on both sides, but it's true that bottom side has almost exclusively passives. However there are a couple of engpasses on the PCB and that's why it seems that we need 4 layers for routing. | |
| Jul 11, 2016 at 8:17 | comment | added | nickagian | @Daniel Yes I have some a PCIe connection and also Ethernet IF, which also means SGMII, RGMII, SSSMII Interfaces. Also for my clock distribution lines it would be better to have controlled impedance, no? | |
| Jul 11, 2016 at 5:25 | comment | added | Neil_UK | Do you need high component denstity, controlled impedance lines, low external EMC, micro-vias for BGAs, buried vias for high density routing, multiple grounds for heat dissipation, top grounds for earthing shielding? Frankly without taking your application into account, you might as well toss a coin between the options you have provided. | |
| Jul 11, 2016 at 1:37 | comment | added | Jasen Слава Україні | putting PWR next to GND gets you a distributed capacitance that can help decouple your power supplies, try not to have the thick fiberglass layer between them. | |
| Jul 10, 2016 at 21:47 | answer | added | user57037 | timeline score: 2 | |
| Jul 10, 2016 at 21:14 | comment | added | Claudio Avi Chami | Can you consider a 10 layer PCB? sig - gnd - sig - sig - gnd - pwr - sig - sig - gnd - sig | |
| Jul 10, 2016 at 21:07 | comment | added | Marcus Müller | To add to the other two comments: It might really be worth considering how many components you have on either side of the board; your 8th layer always being a Signal layer indicates your board has components on both sides, but maybe the bottom side is mainly used for passives/decoupling, so it might be the case that Signal3 or Signal4 could be omitted | |
| Jul 10, 2016 at 20:37 | comment | added | ThreePhaseEel | How many signal routing layers do you actually need? Is 2 for LF and 2 for HF enough, or do you really need 4 HF routing layers? | |
| Jul 10, 2016 at 20:34 | comment | added | Daniel | This depends completely on what you're doing. Are you running PCI Express? That gets kinda touchy about route impedance! C might be a better option. Do you need more space on the outside surfaces for parts? B might be a better option. | |
| Jul 10, 2016 at 20:17 | history | asked | nickagian | CC BY-SA 3.0 |