Timeline for How do I observe a PLL's frequency tracking once the lock has been acquired?
Current License: CC BY-SA 3.0
11 events
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| Sep 30, 2016 at 1:34 | comment | added | Michael Karas | Down vote removed. Thanks for removing all that graphics stuff. | |
| Sep 29, 2016 at 17:22 | comment | added | D.A.S. | Then loop filter is optimized to minimize capture time with minimum overshoot using RF filter BW matched to signal BW and VCXO error < 1-2% jitter | |
| Sep 29, 2016 at 17:14 | comment | added | D.A.S. | A bit of research on PLL capture time vs BW vs lead-lag filters will show you the way. In general, capture range must always exceed initial VCO worst case error, ie. loop bandwidth must be >> offset f error. Therefore Rx f lock is used before Tx or very stable TCXO | |
| Sep 29, 2016 at 17:12 | comment | added | JGalt | @TonyStewart, thank you. I probably need a bit more reading to completely understand this. | |
| Sep 29, 2016 at 17:10 | comment | added | D.A.S. | deleted pdf insert | |
| Sep 29, 2016 at 17:07 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| Sep 29, 2016 at 15:51 | comment | added | D.A.S. | is a link preferred to a subscribed site for reference? at least the graphs will stimulate interested readers to search on their own. I'm not impressed either with site's lack of attachment options. Did you not find any of my comments useful? | |
| Sep 29, 2016 at 15:50 | comment | added | Michael Karas | Besides that it is far too small and nearly unreadable when zooming waaaaaaaaaaaaay in. | |
| Sep 29, 2016 at 15:49 | comment | added | Michael Karas | -1 - Not impressed with the humongus amount of cut / paste graphic info from an outside source. | |
| Sep 29, 2016 at 14:24 | history | edited | D.A.S. | CC BY-SA 3.0 |
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| Sep 29, 2016 at 13:22 | history | answered | D.A.S. | CC BY-SA 3.0 |