2 edited body
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Lets take away some of the magic about bypass caps, by improving the circuit model; 7400 family gates look like this: enter image description here

with shoot-thru current (ignoring currents thru 4Kohm and 1.6Kohm) computed as $$(5v - 3 * Vdiode)/130 Ohm$$ or 5-2.1/130 = 2.9/130 ~ 22 milliAmps.

This gate, available 3-in-one-package, provides high drive (large fanout) and fast speed. Inside a 74195, we don't need all that drive. We do need speed. We'll assume a 2mA shoot-thru per gate (~~15 gates per FF)

schematicschematic

simulate this circuitsimulate this circuit – Schematic created using CircuitLab

We need to store enough charge for 1uS of busy clocking activity. WHY? Why use 1uS? Because big capacitors and long wires will RING, and upset the VDD at the IC, unless dampened. What ringing frequency? 1uH and 1uF produce 0.159KHz. How to dampen?

Use Q=1 [defined as Q = ZL/R = 2(piFringL/R) ] and Fring = 1/2*pisqrt(LC), we find Rdampen = sqrt(L/C). For 1uH and 1uF, need ONE OHM.

Consider this circuit for good control of VDD ringing:

schematic

simulate this circuit

What does Signal Chain Explorer tell us about this 1_ohm dampening?

enter image description here

Surprise? The logic engineer also needs to DESIGN the VDD filtering and the VDD dampening.

Lets take away some of the magic about bypass caps, by improving the circuit model; 7400 family gates look like this: enter image description here

with shoot-thru current (ignoring currents thru 4Kohm and 1.6Kohm) computed as $$(5v - 3 * Vdiode)/130 Ohm$$ or 5-2.1/130 = 2.9/130 ~ 22 milliAmps.

This gate, available 3-in-one-package, provides high drive (large fanout) and fast speed. Inside a 74195, we don't need all that drive. We do need speed. We'll assume a 2mA shoot-thru per gate (~~15 gates per FF)

schematic

simulate this circuit – Schematic created using CircuitLab

We need to store enough charge for 1uS of busy clocking activity. WHY? Why use 1uS? Because big capacitors and long wires will RING, and upset the VDD at the IC, unless dampened. What ringing frequency? 1uH and 1uF produce 0.159KHz. How to dampen?

Use Q=1 [defined as Q = ZL/R = 2(piFringL/R) ] and Fring = 1/2*pisqrt(LC), we find Rdampen = sqrt(L/C). For 1uH and 1uF, need ONE OHM.

Consider this circuit for good control of VDD ringing:

schematic

simulate this circuit

What does Signal Chain Explorer tell us about this 1_ohm dampening?

enter image description here

Surprise? The logic engineer also needs to DESIGN the VDD filtering and the VDD dampening.

Lets take away some of the magic about bypass caps, by improving the circuit model; 7400 family gates look like this: enter image description here

with shoot-thru current (ignoring currents thru 4Kohm and 1.6Kohm) computed as $$(5v - 3 * Vdiode)/130 Ohm$$ or 5-2.1/130 = 2.9/130 ~ 22 milliAmps.

This gate, available 3-in-one-package, provides high drive (large fanout) and fast speed. Inside a 74195, we don't need all that drive. We do need speed. We'll assume a 2mA shoot-thru per gate (~~15 gates per FF)

schematic

simulate this circuit – Schematic created using CircuitLab

We need to store enough charge for 1uS of busy clocking activity. WHY? Why use 1uS? Because big capacitors and long wires will RING, and upset the VDD at the IC, unless dampened. What ringing frequency? 1uH and 1uF produce 0.159KHz. How to dampen?

Use Q=1 [defined as Q = ZL/R = 2(piFringL/R) ] and Fring = 1/2*pisqrt(LC), we find Rdampen = sqrt(L/C). For 1uH and 1uF, need ONE OHM.

Consider this circuit for good control of VDD ringing:

schematic

simulate this circuit

What does Signal Chain Explorer tell us about this 1_ohm dampening?

enter image description here

Surprise? The logic engineer also needs to DESIGN the VDD filtering and the VDD dampening.

1
source | link

Lets take away some of the magic about bypass caps, by improving the circuit model; 7400 family gates look like this: enter image description here

with shoot-thru current (ignoring currents thru 4Kohm and 1.6Kohm) computed as $$(5v - 3 * Vdiode)/130 Ohm$$ or 5-2.1/130 = 2.9/130 ~ 22 milliAmps.

This gate, available 3-in-one-package, provides high drive (large fanout) and fast speed. Inside a 74195, we don't need all that drive. We do need speed. We'll assume a 2mA shoot-thru per gate (~~15 gates per FF)

schematic

simulate this circuit – Schematic created using CircuitLab

We need to store enough charge for 1uS of busy clocking activity. WHY? Why use 1uS? Because big capacitors and long wires will RING, and upset the VDD at the IC, unless dampened. What ringing frequency? 1uH and 1uF produce 0.159KHz. How to dampen?

Use Q=1 [defined as Q = ZL/R = 2(piFringL/R) ] and Fring = 1/2*pisqrt(LC), we find Rdampen = sqrt(L/C). For 1uH and 1uF, need ONE OHM.

Consider this circuit for good control of VDD ringing:

schematic

simulate this circuit

What does Signal Chain Explorer tell us about this 1_ohm dampening?

enter image description here

Surprise? The logic engineer also needs to DESIGN the VDD filtering and the VDD dampening.