Timeline for What's the purpose of the diode at the JFET gate in this Hartley oscillator?
Current License: CC BY-SA 3.0
10 events
| when toggle format | what | by | license | comment | |
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| Sep 23, 2021 at 3:08 | answer | added | Dave Bing | timeline score: 0 | |
| Dec 4, 2018 at 6:00 | history | tweeted | twitter.com/StackElectronix/status/1069833773305466880 | ||
| Dec 4, 2018 at 3:00 | answer | added | Edgar Brown | timeline score: 2 | |
| Dec 4, 2018 at 2:01 | answer | added | mikee | timeline score: 0 | |
| Apr 13, 2017 at 12:32 | history | edited | CommunityBot |
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| Apr 4, 2017 at 8:49 | vote | accept | Buck8pe | ||
| Apr 3, 2017 at 21:49 | comment | added | Buck8pe | @glen it works like a charm at the moment probing Vo with a 10x probe. I'm planning to follow this stage with a JFET buffer, so no worries regarding load. Care to elaborate on the AGC action of D1? | |
| Apr 3, 2017 at 21:39 | comment | added | glen_geek | Loop gain may be too high. Try increasing R1. Or try decreasing C1. Or try an actual load R at Vo - with a small enough load, it'll quit oscillating. The AGC action of D1 can provide a more constant Vo for variations of load R. | |
| Apr 3, 2017 at 20:39 | answer | added | Olin Lathrop | timeline score: 4 | |
| Apr 3, 2017 at 20:33 | history | asked | Buck8pe | CC BY-SA 3.0 |