5 discussed ENOB for 47dB filtering
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The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

And here is the wide-spectrum filtering, assuming the 3 regions of GND are effective, for 0.005 Ohms Switcher Rout; above 3MHz, you get at least 47dB attenuation.

enter image description here

Quiet GND and VDD have to be designed; once quietness is achieved, guard it, protect it, do not expose GND and VDD to trash sources.

How quiet is quiet? 47dB below 100mV ringing of SwitchReg is 200:1 reduction, or 500 microVolts. Given 2.5 volt ADC fullscale, you have dynamic range of 5,000:1, only 12 bits. To reach 16 bits, VDD trash needs 24 dB more filtering. To reach 24 bits (and 24 bits ADCs will be trashed by all aggressors entering the VDD pin), you need 72 dB more filtering, or 2 or 3 more PI filters.

And once 24-bit clean GND and VDD are achieved, you better protect them.

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

And here is the wide-spectrum filtering, assuming the 3 regions of GND are effective, for 0.005 Ohms Switcher Rout; above 3MHz, you get at least 47dB attenuation.

enter image description here

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

And here is the wide-spectrum filtering, assuming the 3 regions of GND are effective, for 0.005 Ohms Switcher Rout; above 3MHz, you get at least 47dB attenuation.

enter image description here

Quiet GND and VDD have to be designed; once quietness is achieved, guard it, protect it, do not expose GND and VDD to trash sources.

How quiet is quiet? 47dB below 100mV ringing of SwitchReg is 200:1 reduction, or 500 microVolts. Given 2.5 volt ADC fullscale, you have dynamic range of 5,000:1, only 12 bits. To reach 16 bits, VDD trash needs 24 dB more filtering. To reach 24 bits (and 24 bits ADCs will be trashed by all aggressors entering the VDD pin), you need 72 dB more filtering, or 2 or 3 more PI filters.

And once 24-bit clean GND and VDD are achieved, you better protect them.

4 added frequency response of PI filter, with various Rsources
source | link

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

And here is the wide-spectrum filtering, assuming the 3 regions of GND are effective, for 0.005 Ohms Switcher Rout; above 3MHz, you get at least 47dB attenuation.

enter image description here

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

And here is the wide-spectrum filtering, assuming the 3 regions of GND are effective, for 0.005 Ohms Switcher Rout; above 3MHz, you get at least 47dB attenuation.

enter image description here

3 added frequency response of PI filter, with varius Rsources
source | link

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

The switchreg will have parasitic ringing at 50X or 100X the switching frequency. Consider 100MHz ringing with 100mV amplitude. With close to ZERO ohms source impedance (the ringing is coming from a Power Circuit, after all).

You could just let that 100MHz ringing, at 100mV, simply enter your MCU. But that will trash any onboard ADC. And the clock-multiply PLL will be wonderfully jittery.

You need 3 regions of GND, to be successful

1) the SwitchReg

2) the filter: bead in series, low-esr cap to GND#2

3) the MCU

These 3 regions of GND should only connect through narrow pieces of foil.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is the noise attenuation of the PI filter shown in the previous schematic, for 4 values of Rout of the SwitcherReg (5 / 0.5/ 0.05 / 0.005 ohms)

enter image description here

Notice the 12dB peaking for 0.005 ohms, the 3dB peaking for 0.05 ohms, then the well-dampened behavior for 0.5 and 5.0 ohms. Thus some discrete resistance between SwitchReg and the PI filter seems useful.

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