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The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in. Inhibit is just an inverted clock input (sans Schmitt trigger). Or add an inverter between 555 and clock in.

In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts and slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor in series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.

Edit: Rough schematic showing supervisor chip ADM803/ADX803

The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in. Inhibit is just an inverted clock input (sans Schmitt trigger). Or add an inverter between 555 and clock in.

In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts and slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor in series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.

Edit: Rough schematic showing supervisor chip ADM803/ADX803, you may want to add a power-on LED or resistor from Vdd to GND to help discharge the 5V faster so it resets reliably on a short power interruption.

The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in. Inhibit is just an inverted clock input (sans Schmitt trigger). Or add an inverter between 555 and clock in.

In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts an slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor in series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.

The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in. Inhibit is just an inverted clock input (sans Schmitt trigger). Or add an inverter between 555 and clock in.

In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts and slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor in series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.

Edit: Rough schematic showing supervisor chip ADM803/ADX803

The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in.

In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts an slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor on series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.

The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in. Inhibit is just an inverted clock input (sans Schmitt trigger). Or add an inverter between 555 and clock in.

In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts an slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor in series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.