The programing with JTAG can be done under any valid MSEL setting (the switch of the photo).

The MSEL setting specifies with way will be programmed automatically a FPGA at power-on (a download from EPCS Flash memory, or an upload by the boot software of the HPS-SoC part), and what configuration format is expected to be read (compressed/uncompressed, encrypted/unencrypted), what it is done with Quartus conversion tools.

at power-on, with way?
MSEL[4..0] 10010 (swith 1-6: ON OFF ON ON  OFF * ) from Flash, compressed/uncompressed
MSEL[4..0] 01010 (swith 1-6: ON OFF ON OFF ON  * ) from HPS software, compressed
MSEL[4..0] 01000 (swith 1-6: ON ON  ON OFF ON  * ) from HPS software, uncompressed
MSEL[4..0] etc

But JTAG works under any valid MSEL setting, so it is not related to your problem:

Try to start the JTAG programing from the beginning (without listed devices).

1. Push in Hardware Setup button -> In Current selected Hardware select DE-SoC [USB-1], and Close the window.

2. Push Autodetect, and at the emerging window select 5CSEMA4

3. The autodetect will make appear two devices listed: SOCVHPS and 5CSEMA4 (Is this happening?)

4. Select 5CSEMA4, right click -> Edit -> Change File

5. Select the sof file generated by compilation, and push open. The name of the device 5CSEMA4 becomes 5CSEMA4U23.

6. Select the Program/Configure checkbox placed at 5CSEMA4U23 Line.

7. Push Start

In the step-4, if you did an Edit -> Add File, probably it altered the device chain in undesired way. I suspect this is what happened you.

With the above you put your program-configuration in the FPGA internal memory, not the EPCS Flash, so it will be temporal.

At future, when one desire to conserve the programing-configuration:

For upload the program-configuration to the Flash Memory, the sof file must be converted to a jic file, plus add to the above step-4 the EPCS128 device, where you will upload the jic file. The FPGA will read it at next power-on if the MSEL permit it (Or with a reset if the board design were included it, what it is not the case).

For store the program-configuration in the FAT partition of the SDCard, used by HPS SoC boot, the sof file must be converted to a rbf file (and the software booting process will upload it to the FPGA).

This means a 'HPS reset' will upload again the programing-configuration to the FPGA if the MSEL setting permit it, and that is why it is used usually the MSEL from Flash when one is testing and uploading with JTAG, as a 'just in case', or at least I see it this way.

The programing with JTAG can be done under any valid MSEL setting (the switch of the photo).

The MSEL setting specifies with way will be programmed automatically a FPGA at power-on (a download from EPCS Flash memory, or an upload by the boot software of the HPS-SoC part), and what configuration format is expected to be read (compressed/uncompressed, encrypted/unencrypted), what it is done with Quartus conversion tools.

at power-on, with way?
MSEL[4..0] 10010 (swith 1-6: ON OFF ON ON  OFF * ) from Flash, compressed/uncompressed
MSEL[4..0] 01010 (swith 1-6: ON OFF ON OFF ON  * ) from HPS software, compressed
MSEL[4..0] 01000 (swith 1-6: ON ON  ON OFF ON  * ) from HPS software, uncompressed
MSEL[4..0] etc

But JTAG works under any valid MSEL setting, so it is not related to your problem:

Try to start with JTAG programing from the beginning (without listed devices).

1. Push in Hardware Setup button -> In Current selected Hardware select DE-SoC [USB-1], and Close the window.

2. Push Autodetect, and at the emerging window select 5CSEMA4

3. The autodetect will make appear two devices listed: SOCVHPS and 5CSEMA4 (Is this happening?)

4. Select 5CSEMA4, right click -> Edit -> Change File

5. Select the sof file generated by compilation, and push open. The name of the device 5CSEMA4 becomes 5CSEMA4U23.

6. Select the Program/Configure checkbox placed at 5CSEMA4U23 Line.

7. Push Start

In the step-4, if you did an Edit -> Add File, probably it altered the device chain in undesired way. I suspect this is what happened you.

With the above you put your program-configuration in the FPGA internal memory, not the EPCS Flash, so it will be temporal.

At future, when one desire to conserve the programing-configuration:

For upload the program-configuration to the Flash Memory, the sof file must be converted to a jic file, plus add to the above step-4 the EPCS128 device, where you will upload the jic file. The FPGA will read it at next power-on if the MSEL permit it (Or with a reset in boards designs what included it, it is not this case).

For store the program-configuration in the FAT partition of the SDCard, used by HPS SoC boot, the sof file must be converted to a rbf file (and the software booting process will upload it to the FPGA).

This means a 'HPS reset' will upload again the programing-configuration to the FPGA if the MSEL setting permit it, and that is why it is used usually the MSEL from Flash when one is testing and uploading with JTAG, as a 'just in case', or at least I see it this way.