Timeline for Birectional I/O pin in verilog
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
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| S May 11, 2020 at 17:44 | history | suggested | Grisha Khachatryan | CC BY-SA 4.0 |
I deleted the unnecessary word "end" and corrected the word "clock" to match the one used in the "always" block.
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| May 11, 2020 at 15:55 | review | Suggested edits | |||
| S May 11, 2020 at 17:44 | |||||
| Jun 4, 2012 at 1:43 | comment | added | vicatcu | @sybreon heh, I just used Eagle schematic capture to hack a drawing together. | |
| Jun 4, 2012 at 0:49 | comment | added | sybreon | what software are u using to produce that synthesis output? | |
| Jun 3, 2012 at 18:46 | vote | accept | John Burton | ||
| Jun 3, 2012 at 18:38 | comment | added | vicatcu | The updated code (and picture) will pass io_port to data_out when direction is low and will pass data_in to io_port (and data_out one cycle later) when direction is high. | |
| Jun 3, 2012 at 18:35 | history | edited | vicatcu | CC BY-SA 3.0 |
added 165 characters in body
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| Jun 3, 2012 at 18:19 | comment | added | vicatcu | @JohnBurton I changed the verilog to be a little more like I think what you were going for. | |
| Jun 3, 2012 at 18:15 | comment | added | John Burton | Ah I see. Thank you.I completely forgot about z states. Although this will always set data_in to be the data I'm sending won't it and not the value of the pin? | |
| Jun 3, 2012 at 18:15 | history | edited | vicatcu | CC BY-SA 3.0 |
added 104 characters in body
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| Jun 3, 2012 at 18:08 | history | answered | vicatcu | CC BY-SA 3.0 |