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In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

Here the paths available from input to output and corresponding delays are:

1. Input-A1-A2-T2-output : 20 ns
2. Input-A1-T1-T2-output: 25 ns
3. Input-A1-T1-A2-T2-output: 30 ns
4. Input-T0-T1-T2-output: 30 ns
5. Input-T0-A1-A2-T2-output: 30 ns
6. Input-T0-T1-A2-T2-output: 35 ns
7. Input-T0-A1-T1-T2-output: 35 ns
8. Input-T0-A1-T1-A2-T2-output: 40 ns

So the output can change at 20 ns, 25 ns, 30 ns and at 40 ns because of the input applied at 0 ns. Hence the valid stable output comes only after 40 ns. Hence 40 ns is the propagation delay here.

In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

Here the paths available from input to output and corresponding delays are:

1. Input-A1-A2-T2-output : 20 ns
2. Input-A1-T1-T2-output: 25 ns
3. Input-A1-T1-A2-T2-output: 30 ns
4. Input-T0-T1-T2-output: 30 ns
5. Input-T0-A1-A2-T2-output: 30 ns
6. Input-T0-T1-A2-T2-output: 35 ns
7. Input-T0-A1-T1-T2-output: 35 ns
8. Input-T0-A1-T1-A2-T2-output: 40 ns

So the output can change at 20 ns, 25 ns, 30 ns, 35 ns and at 40 ns because of the input applied at 0 ns. Hence the valid stable output comes only after 40 ns. Hence 40 ns is the propagation delay here.

In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

So it can be calculated by finding out critical path, the path from input to output which has maximum delay. The corresponding delay is propagation delay.

Here the paths available from input to output and corresponding delays are:

1. Input-A1-A2-T2-output : 20 ns
2. Input-A1-T1-T2-output: 25 ns
3. Input-A1-T1-A2-T2-output: 30 ns
4. Input-T0-T1-T2-output: 30 ns
5. Input-T0-A1-A2-T2-output: 30 ns
6. Input-T0-T1-A2-T2-output: 35 ns
7. Input-T0-A1-T1-T2-output: 35 ns
8. Input-T0-A1-T1-A2-T2-output: 40 ns

So the output can change at 20 ns, 25 ns, 30 ns and at 40 ns because of the input applied at 0 ns. Hence the valid stable output comes only after 40 ns.

In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

Here the paths available from input to output and corresponding delays are:

1. Input-A1-A2-T2-output : 20 ns
2. Input-A1-T1-T2-output: 25 ns
3. Input-A1-T1-A2-T2-output: 30 ns
4. Input-T0-T1-T2-output: 30 ns
5. Input-T0-A1-A2-T2-output: 30 ns
6. Input-T0-T1-A2-T2-output: 35 ns
7. Input-T0-A1-T1-T2-output: 35 ns
8. Input-T0-A1-T1-A2-T2-output: 40 ns

So the output can change at 20 ns, 25 ns, 30 ns and at 40 ns because of the input applied at 0 ns. Hence the valid stable output comes only after 40 ns. Hence 40 ns is the propagation delay here.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Usually the propagation delay is calculated by finding out critical path, the path from input to output which has maximum delay. The corresponding delay is propagation delay.

Here the critical path from input to output is has two and gates and 3 flipflops. So the corresponding delay = 25+310 = 40 ns.

In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

So it can be calculated by finding out critical path, the path from input to output which has maximum delay. The corresponding delay is propagation delay.

Here the paths available from input to output and corresponding delays are:

1. Input-A1-A2-T2-output : 20 ns
2. Input-A1-T1-T2-output: 25 ns
3. Input-A1-T1-A2-T2-output: 30 ns
4. Input-T0-T1-T2-output: 30 ns
5. Input-T0-A1-A2-T2-output: 30 ns
6. Input-T0-T1-A2-T2-output: 35 ns
7. Input-T0-A1-T1-T2-output: 35 ns
8. Input-T0-A1-T1-A2-T2-output: 40 ns

So the output can change at 20 ns, 25 ns, 30 ns and at 40 ns because of the input applied at 0 ns. Hence the valid stable output comes only after 40 ns.