Timeline for Why are sum-of-products implementations more popular than product-of-sums implementations?
Current License: CC BY-SA 3.0
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| Sep 15, 2015 at 20:49 | comment | added | supercat |
It's worth noting that (a and b) or (c and d) is equivalent to (a nand b) nand (c nand d).
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| Jun 23, 2012 at 22:28 | comment | added | W5VO | @StevenRoose In a standard CMOS process, yes. PFETs are usually worse than NFETs, so the PFETs must be larger to match the NFET pull-downs. With a NOR gate, two PFETs are in series and should be doubled in size. For a NAND gate, you would have an active area of say 8-10 units, and a NOR gate would have an area of maybe 14-20 depending on the relative strength of the PFETs and NFETs. | |
| Jun 23, 2012 at 18:19 | comment | added | Steven Roose | Hmm, I read how AND and OR gates can be realized with NAND gates, yes. So probably an AND gates requires less NAND's than an OR. Which seems reasonable :P But are NAND's cheaper than NOR's? | |
| Jun 23, 2012 at 16:47 | history | answered | Shamtam | CC BY-SA 3.0 |